Intel Corporation

Apple Inc.

International Business Machines Corporation

Guy G Sotomayor

Guy M Therien

Arijit Biswas

Michael D Powell

Venkatesh Ramani

Krishnakanth Venkata Sistla

Ankush Varma

Robert E Gough

David Gerard Conroy

Tod F Schiff

Eric J DeHaemer

Andrew D Henroid

Keith Alan Cox

Michael F Culbert

Daniel Heller

Alexander Gendler

Kristoffer Fleming

David W Browning

Vivek Garg

Dean A Mulla

Umesh Suresh Vaishampayan

Mark Edward Dean

Ashish V Choubal

Joseph Sokol, Jr

Ronald Lynn Rockhold

Vasudev Bibikar

Arvind Raman

James William Van Fleet

Rahul Agrawal

Christopher G Peak

James Michael Magee

Daniel S Heller

Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

Systems, methods and devices for determining work placement on processor cores

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

Dynamically updating logical identifiers of cores of a processor

Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Systems, methods and devices for work placement on processor cores

The present disclosure is directed to logging random 'chirps' of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.

Internet of things electronic signal aggregator and repeater

In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

Controlling telemetry data communication in a processor

The disclosed embodiments provide a system that facilitates power management in a multi-core processor. During operation, the system detects a change related to a number of active processor cores in the multi-core processor. (Within this system, a given processor core can reside in an active state, wherein the given processor core can draw an active power, or alternatively in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power.) In response to detecting the change, the system computes a new current limit Ifor the multi-core processor based on the number of active and constrained processor cores. Finally, the system communicates Ito a power-management mechanism within the multi-core processor. This enables the power-management mechanism to use Ito account for power saved by the constrained processor cores when the multi-core system is subsequently determining whether to change its operating frequency.

Facilitating power management in a multi-core processor

A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.

System and method for adjusting power usage to reduce interrupt latency

A system and method are described for utilizing task urgency information when making power management decisions. For example, one embodiment of a method for managing power states of a processor comprises: executing a first power management state machine based on a first urgency level associated with a first task; detecting the execution of a second task having a second urgency level associated therewith; if the second urgency level is greater than the first urgency level, then executing a second power management state machine associated with the second urgency level.

System and method for managing clock speed based on task urgency

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San Jose, CA, United States of America

Guy G Sotomayor