Compaq Computer Corporation, Inc.

Guy E McSwain

Paul R Culley

Michael J Collins

Dale J Mayer

Jeffrey C Stevens

John A Landry

Christopher C Wanner

A cache memory system utilizing asynchronous/synchronous burst counter circuitry which lessens the need for expensive, high speed data SRAM to achieve zero wait-state operation. The burst counter circuitry takes advantage of the fact that a read address is present on the address bus approximately one-halfway through the initial bus cycle (T1) during a burst read. Unlike synchronous prior art burst counters, burst counter circuitry according to the invention is configured to forward the address to asynchronous address decoders as soon as it is present, rather than waiting for the next rising edge of the processor clock. For accesses to the first cache line, the timing budget therefore includes the first complete clock cycle of a burst read (T2) plus an extra half-clock cycle from T1. The extra time is utilized to retrieve data from the data SRAM core for provision to the processor data bus at the end of the bus cycle T2. Subsequent accesses are controlled by the burst counter in a synchronous fashion that corresponds to a processor specific burst ordering scheme. Due in part to the interleaved nature of the data SRAM, subsequent burst accesses are allotted almost 2 full clock cycles per data access. Thus, the shortest time in which the data SRAM must respond to an access request is the initial one and one-half clock cycles. Slower and less expensive data SRAMs can therefore be used to provide a cache memory capable of zero wait state operation.

Cache memory using unique burst counter circuitry and asynchronous

An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Arrangement of DMA, interrupt and timer functions to implement

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Cypress, TX, United States of America

Guy E McSwain