Altera Corporation

Guy Dupenloup

Khai Nguyen

Tzung-Chin Chang

Gopinath Rangan

Ninh D Ngo

Wira Gunawan

Zunghang Yu

A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit&#xd7;N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit&#xd7;N/2-bit multipliers. Because the same circuitry can be used to serve as both an N&#xd7;N multiplier and as dual N/2&#xd7;N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.

Verifiable multimode multipliers

The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.

Apparatus and method for RTL modeling of a register

An RTL representation for a LAB is generated. A full chip RTL model is then generated using a plurality of the LAB RTLs. Using the full chip RTL model, a full chip simulation of the PLD chip is performed to verify and debug the electronic design.

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Redwood City, CA, United States of America

Guy Dupenloup