Lsi Logic Corporation

Guy Dupenloup

Kevin C Cleereman

A method of generating synthesis scripts to synthesize integrated circuit (IC) designs described in a generic netlist into a gate-level description includes the steps of identifying hardware elements in a generic netlist, determining key pins for each of the identified hardware elements, extracting design structure and hierarchy from the generic netlist, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design, and generating script to cause a logic synthesis tool to repeat these bottom-up and top-down applications until constraints are satisfied.

Automatic synthesis script generation for synopsys design compiler

A method of efficiently characterizing modules of an integrated circuit (IC) design using a logic synthesis tool comprising the steps of defining a list of instances of the modules to characterize, and characterizing entire modules of said list of instances of the modules using a single invocation of characterize command of the logic synthesis tool.

Efficient top-down characterization method

A method of synthesizing integrated circuit (IC) design having DesignWare components comprising the steps of initially mapping DesignWare components, revising DesignWare component structure, ungrouping DesignWare components, and re-synthesizing DesignWare components. The step of initially mapping is performed using elaborate command and compile command of a logic synthesis tool. The step of ungrouping DesignWare components involves dissolving DesignWare modules to be merged with surrounding logic.

Method of handling macro components in circuit design synthesis

A method of generating synthesis scripts to synthesize integrated circuit (IC) designs in RTL level description into gate-level description comprising the steps of identifying hardware elements in the RTL code, determining key pins for each of said identified hardware elements, extracting design structure and hierarchy from the RTL code, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design and generating script to cause a logic synthesis tool to repeat said bottom-up and said top-down applications until certain predetermined constraints are satisfied.

RTL analysis for improved logic synthesis

A method of determining circuit characteristics of an integrated circuit design defined by RTL code, said method comprising the steps of identifying hardware elements in the RTL code, determining key pins for said identified hardware elements, and extracting critical design structure from the RTL code. The hardware elements identified include flipflops, latches, tristate buffers, bidirectional buffers and memories. The critical design structures include design hierarchy and nets, including clock nets, multiply-driven nets, reset nets, and RAM write enable nets.

RTL analysis tool

A method of determining circuit characteristics of an integrated circuit design as defined by a generic netlist comprising the steps of identifying hardware elements in the generic netlist, determining key characteristics for each of said identified hardware elements, determining interconnections of said identified hardware elements, and detecting the degree of conformity of said identified hardware elements, said key characteristics, and said interconnections to predetermined configurations. The systems further identifies all cells in the generic netlist, determines for each cell the type of cell, accumulates cell types and cell type counts, and notifies an operator of said accumulated values.

Netlist analysis tool by degree of conformity

A method of fabricating an integrated circuit chip (IC), said method comprising the steps of defining the IC at the RTL code level, translating said RTL code into a generic netlist description, generating logic synthesis tool scripts based on said generic netlist description, and executing said logic synthesis tool scripts to synthesize the RTL code. The step of generating logic synthesis tool scripts comprises the substeps of identifying hardware elements and structure of the IC design, determining interrelationships between said identified hardware elements and structures, and generating logic synthesis tool scripts to synthesize said identified hardware elements to netlists as a function of said hardware elements and said interrelationships.

VDHL/Verilog expertise and gate synthesis automation system

A method of translating an integrated circuit chip (IC) design as represented by RTL code to generic netlist using a logic synthesis tool comprising the steps of parsing the RTL code using analyze command of the logic synthesis tool, building the generic netlist using evaluate command of the logic synthesis tool, and recording the generic netlist to a dump file outside the logic synthesis tool. The dump file comprises characteristics of each input ports of current design, characteristics of each output ports of the current design, and characteristics of each cells of the current design.

Method of accessing the generic netlist created by synopsys design compilier

A method of determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design comprising the steps of determining source pins of the nets of the buffering tree, determining fanout of each of said source pins, determining active edges and active levels of each of said source pins, and presenting said source pins, said fanout, and said active edge on a report.

Buffering tree analysis in mapped design

A method of synthesizing integrated circuit chip (IC) designs having clock signals defined internal to a module comprising the steps of mapping the IC design to a target technology with the internal clock defined, removing definitions of the internal clock, re-synthesizing the IC design, and re-defining the internal clock using new names of clock sources.

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Marly le roi, France

Guy Dupenloup