Infineon Technologies Ag

Gustav Beckmann

Martin Schrems

Emmerich Bertagnolli

Helmut Klose

Jens-Uwe Sachse

Moritz Haupt

Anke Krasemann

Alexandra Lamprecht

Dietmar Ottenw&auml;lder

Michael Bianco

A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor

A method for manufacturing a trench capacitor uses a low-pressure gas phase doping for forming a buried plate as a capacitor plate. The use of the low-pressure gas phase doping reduces process costs and improves capacitor properties.

Method for manufacturing a trench capacitor

Growing community of inventors

Radeburg, Germany

Gustav Beckmann