Arm Limited

International Business Machines Corporation

Motorola Corporation

Gus Wai-Yan Yeung

Yew Keong Chong

George McNeil Lattimore

Andy Wangkun Chen

Sriram Thyagarajan

Bo Zheng

Fakhruddin Ali Bohra

Terry Lee Leasure

Marlin Wayne Frederick, Jr

Michael Kevin Ciraula

Robert Anthony Ross, Jr

Hemangi Umakant Gajjewar

Martin Jay Kinkade

Younes John Lotfi

Tom Shore

Wang-Kun Chen

Sachin Satish Idgunji

Brian Tracy Cline

Donald George Mikan, Jr

Lalit Gupta

Shri Sagar Dwivedi

Xiaoqing Xu

Paul Christopher De Dood

Daniel J Albers

Jerry Chaoyuan Wang

David William Granda

Bal S Sandhu

Mudit Bhargava

Gary L Miller

Michael Filippo

Robert J Reese

Jose Angel Paredes

John Beck

Edward John Silha

Larry Edward Thatcher

Rahul Mathur

Frank Guo

Paul Stanley Hughes

Jungtae Kwon

Albert Y Chang

James Dennis Dodrill

Sanjay Mangal

Paul Darren Hoxey

Srinivasan Srinath

David Anthony New

Andrew John Sowden

Gary Robert Waggoner

Binta Minesh Patel

Thanusree Achuthan

Amarnath Shanmugam

Jacek Wiatrowski

David John Willingham

Chris P Ahrens

Yanbin Jiang

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

Sylvia Xiuhui Li

Yew-Keong Chong

Brian Douglas Ngai Lee

Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

Pulse stretcher circuitry

Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

Computer implemented system and method for generating a layout of a cell defining a circuit component

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

Port modes for use with memory

Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

Location-based optimization for memory systems

Within a memorycomprising an arrayof bit cellswrite driver circuitryuses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistorsare driven by column select circuitry. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumpsare employed within the column select circuitryto achieve these boosted levels for the columns select signal.

Memory circuitry using write assist voltage boost

A memoryincludes a regular array of storage elements. A regular array of write multiplexersis provided outside of the regular array of storage elements. The storage element pitch is matched to the write multiplexer pitch. The write multiplexerssupport a plurality of write ports. When forming a memory design, a given instance of an array of write multiplexersmay be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array

Memory with multiple write ports

Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

Retention voltages for integrated circuits

A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

Access suppression in a memory device

Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

Low power input gating

A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

Memory device and method of controlling leakage current within such a memory device

A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Memory access control in a memory device

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Austin, TX, United States of America

Gus Wai-Yan Yeung