Freescale Semiconductor,inc.

Nxp Usa, Inc.

Gus P Ikonomopoulos

Thang Q Nguyen

Kun Xu

Jose Melanio Nunez

Harold M Martin

Tommi Jorma Mikael Jokinen

Prakashkumar Govindbhai Makwana

Jatin Vinay Pai

Upon receiving a request () in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device () allocates, to the ordered request, entries in a first ordered queue (e.g.,) and a first static queue (e.g.,) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g.,) and a second static queue (e.g.,) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue () for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.

Method for reordering out of order responses from decomposed requests in bridge IP

Systems and methods for operating a DMA unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. A second number of bytes to reach a read address alignment is determined. In a first data transfer, a third number of bytes substantially equal to the first number of bytes plus the second number of bytes are transferred. In subsequent data transfers of the read job, the first number of bytes are transferred to the data buffer. After the third number of bytes are transferred to the data buffer, a fourth number of bytes from the data buffer are transferred to a destination.

Direct memory access (DMA) unit with address alignment

A data processing device includes an interconnect controller operable to manage the communication of information between modules of the data processing device via an interconnect. In response to a transaction request the interconnect controller selects a tag value from a set of available tag values, assigns the tag to the transaction and reserves the tag value so that it is unavailable for assignment to other transactions. If an expected response to the transaction request is not received within a designated amount of time, the transaction enters a timed-out state and the interconnect controller locks the tag value, so that it remains unavailable for assignment to other transactions until an unlock event, such as a request from software.

Interconnect controller for a data processing device with transaction tag locking and method therefor

A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Read stacking for data processor interface

A maximum timeout time for a communication between devices is determined. A time period is determined for a plurality of time zones based upon the maximum timeout time. A current time zone is updated every time period. A timeout zone for an outstanding transaction is associated with a first time zone to indicate when the outstanding transaction will timeout if not completed. In one embodiment, the time period for each time zone is approximately equal to the maximum timeout period divided by a predetermined number of time zones, which may be the total number of time zones, e.g. eight or sixteen.

Growing community of inventors

Lakeway, TX, United States of America

Gus P Ikonomopoulos