Advanced Micro Devices Corporation

Network Equipment Technologies, Inc.

Bay Networks, Inc.

Inviscid Networks, Inc.

Gururaj Singh

Peter J Newman

Amar S Gupta

Willie T Glover

Michael Yip

Jan Bialkowski

Randy Ryals

H Earl Ferguson

Farzin Firoozmand

Jeff Prince

Clifford James Buckley

Ronald C Laugesen

P Venkitakrishnan

A method of filtering packets having a class. The method includes the steps of accessing a table comprised of entries that include an indication to which class a given entry applies. Then there is the step of searching the entries until an entry whose class indication corresponds to a current class of the packet. Next there is the step of forwarding a frame associated with the entry whose class indication corresponds to the class of the packet. A data communication apparatus. The apparatus includes a mechanism for routing or switching packets. The apparatus includes a memory having information for routing or switching the packets. The apparatus includes a mechanism for compaction of information in the memory which removes redundancies in the information.

Packet filtering method

Reactive congestion control in an asynchronous transfer mode (ATM) network where the network is formed by the interconnection of nodes each including a forward path for transfer of information from source to destination through the network and a return path for returning congestion control signals. Each source includes a modifiable issue rate unit which issues forward information signals at different rates for virtual channels in response to the presence and absence of congestion signals received on the return path.

Method and apparatus for reactive congestion control in an asynchronous

In a segmentation and reassembly module in a local area network switch module, a method and apparatus for storing fixed length data cells received from an ATM network in a plurality of memory buffers during the reassembly of the data cells in to a variable length data packet to be transmitted on an attached local area network.

Memory architecture for a local area network module in an ATM switch

A communication unit for concurrently processing cells in an asynchronous transfer mode (ATM) network. Packets are segmented into a plurality of cells concurrently for a plurality of channels for transmission over the (ATM) network. Cells received from the ATM network are reassembled concurrently for the plurality of channels. Pipelined processing units are employed for segmentation and for reassembly each having logic control, control memory, and data memory. The segmentation unit control memory stores two-dimensional queues with first dimension rate queues for queueing descriptors for cells of different channels having cells to be transmitted and with second dimension channel queues for each channel having a cell descriptor in the rate queue.

Concurrent multi-channel segmentation and reassembly processors for

The standard FDDI priority algorithm is implemented by programming Token Holding Time (THT) threshold values for asynchronous service either in an increasing or decreasing order as a function of token holding time. If the thresholds are programmed in a decreasing order, all higher priority data is sent to the network before any lower priority data is sent. If the thresholds are programmed in an increasing order, highest priority data is sent first, until the unexpired token holding time falls below the threshold value for that priority; the next lower priority level data then is transmitted, and so on. Accordingly, at least some data of all priority assignments pending for transmission are sent to the medium during each token capture.

Method of and system for implementing multiple levels of asynchronous

An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The design of the general-purpose DSP is readily expandible to accomodate additional circuit elements and/or more signals to be processed in parallel.

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San Jose, CA, United States of America

Gururaj Singh