Intel Corporation

Gururaj Shamanna

Stefan Rusu

Tessil Thomas

Phani Kumar Kandula

Narayanan Natarajan

Jagadeesh Chandra Salaka

Harishankar Sahu

Naveen Kumar M

Sankalan Prasad

Mandar R Ranade

Abhishek A Sharma

Iqbal Rajwani

Derek T Bachand

Eric A Karl

Pascal Meinerzhagen

Zheng Guo

Chih-Hung Chung

Sravan K Puchakayala

Purna C Nayak

Abhishek Chouksey

Madhusudan Rao

Mitesh Goyal

Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.

Apparatus and method to optimize sense-amp enable pulse-width in SRAM arrays

An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Keeper-free integrated clock gate circuit

A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.

Low power clock gate circuit

Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Apparatus for adaptive write assist for memory

Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Apparatus and method for reducing leakage power of a circuit

A method and apparatus for avoiding tag compares when writing to a cache. In a cache hierarchy, location information of the cache entries are linked and supplied to the other caches, during caching of the data from memory. When the processor is ready to update the content of the memory location, the location information loaded into a write buffer allows the write buffer to update the cache(s), without the need for tag comparisons to determine if particular entries are present. The avoidance of the tag compare operation during cache update saves a clock cycle, so that overall processor performance is improved.

Avoiding tag compares during writes in multi-level cache hierarchy

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Austin, TX, United States of America

Gururaj Shamanna