Intel Corporation

Guruprasad Settuvalli

Eugene Gorbatov

Russell Jerome Fenger

Rajshree Chabukswar

Monica Gupta

Eliezer Weissmann

Atsuo Kuwahara

Hisham Abu Salah

Ahmad A Samih

Muhammad Abozaed

Vijay Dhanraj

Shadi T Khasawneh

Mukund Ramakrishna

Balaji Masanamuthu Chinnathurai

Christine M Lin

Sumant Tapas

Meghana Gudaram

Raj Kumar Subramaniam

Rajshree Arun Chabukswar

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Operating system assisted prioritized thread execution

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

Growing community of inventors

Hillsboro, OR, United States of America

Guruprasad Settuvalli