Advanced Micro Devices Corporation

Microsoft Technology Licensing, LLC

Globalfoundries Inc.

Gurupada Mandal

Sang Hoo Dhong

John J Wuu

Hyun-Jin Cho

Jung-Suk Goo

Jin Haeng Cho

In one example, an electrostatic discharge (ESD) protection circuit includes a first power supply having a first supply voltage, wherein the first power supply is connected to a first node. The ESD protection circuit also includes a second power supply having a second supply voltage, wherein the second power supply is connected to the first node. The ESD protection circuit also includes an inverter that receives an input voltage from the first node and produces an output voltage. An ESD discharge device receives the output voltage and provides a discharge path for the first power supply and the second power supply if the output voltage indicates occurrence of an ESD event affecting the first power supply or the second power supply.

Electrostatic discharge circuit for cross domain ESD protection

A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.

Dynamic random access memory (DRAM) cells and methods for fabricating the same

An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.

Memory device and method thereof

A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.

A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

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Gurupada Mandal