Lsi Logic Corporation

Lsi Corporation

Gurumani Senthil

Gary Scott Delp

George Wayne Nation

Vardhaman Veturi

Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.

Methods and structures for improved buffer management and dynamic adaptation of flow control status in high-speed communication networks

Methods and structures for improved buffer management and dynamic adaption of flow control status in high-speed communication networks

A method for reducing latency in conversions from a SMII (Serial Media Independent Interface) to a MII (Media Independent Interface). The method involves generating receive and transmit clock signals from a physical layer device; generating receive and transmit clock signals at a media access controller; and synchronizing the clock signals at the media access controller and the clock signals at the physical layer device such that MII clocks are generated from the SMII and a synchronization signal of the SMII is always delayed 8 nsec from a positive edge of the MII clock.

Minimal latency serial media independent interface to media independent interface converter

A method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) partitions. Upon receiving an address for a particular memory location, address translation circuitry according to the present invention effectively converts the address to a floating point number. The address translation circuitry then divides the received address by three to determine which word of memory&mdash;and which byte&mdash;is being addressed. In particular, the quotient of the division process provides the word address, while the remainder provides the byte offset. Memory addressed by the present invention may be organized into &ldquo;words&rdquo; of varying length. For example, each &ldquo;word&rdquo; may be ninety-six bits wide, with partitions of thirty-two bits each. In this embodiment, the remainder of the division process identifies a particular thirty-two bit partition. The address translation circuitry performs the division by three operation by multiplying the floating point number by a binary value of approximately one third (0.010101 . . . ). In one embodiment, the two most significant bits of the fractional portion of the result equal the required byte offset (e.g., 0&equals;00 binary; 1&equals;01 binary and 2&equals;10 binary). The binary multiplication process involves shifting and adding of the floating point number. Shifting of the floating point number is equivalent to selecting different portions of the received address for addition. Combinational logic (i.e., logic that is not clocked) may be used to perform the translation process. In this manner, address translation may be completed in as few as a single clock cycle.

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San Jose, CA, United States of America

Gurumani Senthil