International Business Machines Corporation

Gurumakonda R Srinivasan

John S Lechaton

Shashi D Malaviya

Dominic Joseph Schepis

Narasipur G Anantha

Santosh Prasad Gaur

Philip M Pitner

Harsaran S Bhatia

Joseph M Mosley

Herbert I Stoller

Jack A Dorler

James L Walsh

Richard R Konian

Joseph R Cavaliere

A method of integrated circuit fabrication and the resulting integrated circuit wherein areas of recessed oxide isolation surround active device regions and the bird's head and bird's beak formed during formation of the recessed oxide regions is eliminated by forming a deep dielectric isolation trench directly over the bird's head. A very thin epitaxial layer can be provided over the active device regions of the integrated circuit. Preferably, the thin epitaxial layer is selectively grown only over active device regions. Also, in later manufacturing steps, metal is deposited in direct registration with contact areas.

Semiconductor device and process

There is described a process for making a high performance NPN bipolar transistor functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body wherein the transistor includes an N+ subcollector, an N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through region, an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region located extending from the major surface and adjacent to the emitter region. The extrinsic base preferrably completely surrounds or rings the emitter region. A mask is formed above the major surface and the mask has openings therein only in the areas above major portions of the extrinsic base regions. A P+ type region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made to the elements of the transistor and the elements are connected in a current switch logic circuit. The use of the high conductivity P+ region in the extrinsic base region closely adjacent to the emitter substantially reduces the extrinsic base resistance. Since the extrinsic base region resistance is reduced, it is possible to reduce the size of the emitter area. Independent doping in the extrinsic base through the mask openings also allows independent control of the intrinsic and extrinsic base resistances. The result of these changes substantially increase the performance of bipolar transistor integrated circuits for current switch logic applications.

High performance integrated circuit having modified extrinsic base

A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the mnocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

Total dielectric isolation for integrated circuits

A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body. The transistor includes an N+ subcollector, and N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region extending from the major surface and adjacent to the emitter region. The extrinsic base completely surrounds the emitter region. A mask is formed above the major surface having openings only above major portions of the extrinsic base regions. A P+ region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made and the elements are connected in a current switch logic circuit. The use of high conductivity P+ region in the extrinsic base region closely adjacent to the emitter reduces the extrinsic base resistance. Independent doping in the extrinsic base through the mask openings allows independent control of the intrinsic and extrinsic base resistances. These changes increase the performance of bipolar transistor integrated circuits for current switch logic applications.

Method for making a high performance transistor integrated circuit

A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.

Method and resulting structure for selective multiple base width

A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the monocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The bipolar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitter is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter is etched. and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

Method for making a base etched transistor integrated circuit

A method for making a filamentary pedestal transistor is disclosed in which epitaxial silicon is formed selectively above portions of a subcollector through the use of laser radiation. A single crystal substrate, having a subcollector of higher impurity concentration, is covered by an oxide mask which is apertured at two locations above the subcollector. Polycrystalline silicon is deposited over the apertured oxide mask. The structure is exposed to laser radiation of suitable energy level and wavelength to selectively convert the polycrystalline silicon to epitaxial monocrystalline silicon within and above the oxide apertures. The transistor is completed by conventional techniques to form base, emitter and collector reach-through regions.

Selective epitaxy method using laser annealing for making filamentary

A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.

Selective epitaxy method for making filamentary pedestal transistor

A method is described for depositing silicon epitaxy with very low defect levels and sharp dopant profiles which are suitable for fabricating high performance, shallow device structures. The epitaxial layer envisioned is less than about 2 microns in thickness. The layer is deposited upon a silicon substrate that has subcollector buried layers therein of above about 1.times.10.sup.20 N type impurity. The substrate is baked at between about 1120.degree. to 1180.degree. C. in hydrogen and then the epitaxial layer is formed using silicon tetrachloride and a temperature of between about 1000.degree. to 1100.degree. C. thereon.

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Poughkeepsie, NY, United States of America

Gurumakonda R Srinivasan