Taiwan Semiconductor Manufacturing Comp. Ltd.

Guru Prasad

Sachin Kumar

Ta-Pen Guo

Osamu Takahashi

Yu Hsi Wang

A semiconductor device includes a first power rail and a second power rail; a third power rail and a fourth power rail, the fourth power rail aligned with the third power rail in a column direction; a first cell arranged between the first power rail and the second power rail; a second cell arranged between the first power rail and the third power rail; and a dummy fin structure extending in the row direction and overlapped with the fourth power rail, wherein the dummy fin structure is configured as a non-functional device. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.

Semiconductor device including standard cells with combined active region

Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.

Systems and methods for multi-bit memory with embedded logic

Split stack triple height cells and methods of generating layouts of same are described herein. The structure includes a circuit formed within three stacked rows. The circuit includes a first stage having a first plurality of electrical components and a second stage having a second plurality of electrical components. The first row includes a first electrical component of the first plurality of electrical components within a top portion of the first row. A first electrical component of the second plurality of electrical components is within a bottom portion of the first row and a top portion of the second row. A second electrical component of the second plurality of electrical components is within a top portion of the third row and a bottom portion of the second row. A second electrical component of the first plurality of electrical components is within a bottom portion of the third row.

Split stack triple height cell

A semiconductor device includes a first and a second power rails extending in a row direction, a third power rail extending in the row direction between the first and second power rail, and a first cell arranged between the first second power rails. A cell height of the first cell in a column direction perpendicular to the row direction is equal to a pitch between the first and second power rails. The semiconductor device also includes a second cell arranged between the first and third power rails. A cell height of the second cell in the column direction is equal to a pitch between the first and third power rails. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.

Systems and method are provided for automating design of an integrated circuit. In an embodiment, an integrated circuit design file is received that specifies logic elements. A plurality logic elements are identified that share a common input signal. A determination is made that the each of plurality of logic elements include a series of transistors. Upon said determining, the integrated circuit design is modified by identifying first and second transistors for a first of the logic elements, identifying first and second transistors for a second of the logic elements, deleting the second transistor of the second logic element, and routing an output of the first transistor of the second logic element to an input of the second transistor of the first logic element. The modified integrated circuit design is stored in a non-transitory computer-readable medium.

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Austin, TX, United States of America

Guru Prasad