Micron Technology Incorporated

Micron Semiconductor, Inc.

Round Rock Research, LLC

Other

Ovonyx Memory Technology, LLC

Applied Materials, Inc.

Intel Corporation

Mosaid Technologies Corporation

Lodestar Licensing Group LLC

Boise Technology, Inc.

Gurtej S Sandhu

Cem Basceri

Trung Tri Doan

John A Smythe

Sujit Sharan

Garo Jacques Derderian

Pierre C Fazan

Durai Vishak Nirmal Ramaswamy

Scott E Sills

Ravi T Iyer

Jun Liu

Roy Edward Meade

Bhaskar Srinivasan

Chandra V Mouli

Guy T Blalock

Neal R Rueger

Zhiping Yin

Howard E Rhodes

Shubneesh Batra

Weimin Li

Donald L Westmoreland

Vishnu Kumar Agarwal

Kirk D Prall

Sanh D Tang

Anand Srinivasan

Kamal M Karda

Witold Kula

Kunal R Parekh

Nishant Sinha

Mirzafer K Abatchev

Wayne I Kinney

D Mark Durcan

F Daniel Gealy

Warren M Farnworth

Randhir P Thakur

Luan C Tran

H Montgomery Manning

Mark R Visokay

Ardavan Niroomand

Tyler A Lowrey

Richard J Hill

Stephen J Kramer

Dan Gealy

Philip J Ireland

Eugene P Marsh

Chris M Carlson

Ross S Dando

Mike P Violette

Martin Ceredig Roberts

Fernando N Gonzalez

Haitao Liu

John K Zahurak

Dan B Millward

Paul A Morgan

Werner Juengling

Terry L Gilton

John K Lee

Yauh-Ching Liu

Ammar Derraa

Anton J deVillers

John T Moore

Randhir P S Thakur

Alan R Reinberg

Roger R Lee

Mark W Kiehlbauch

Si-Woo Lee

Brent Keeth

Mei Yin Chang

Shyam Surthi

Max F Hineman

Akira Goda

Li Li

Brian A Vaartstra

David H Wells

J Brett Rolfson

Scott G Meikle

Mark Fischer

Lifang Xu

William Arthur Stanton

Scott L Light

Mark E Tuttle

David A Cathey

Scott James Derner

Hiroki Fujisawa

Charles L Ingalls

Krishna Kumar Parat

Thomas Arthur Figura

Thomas M Graettinger

Kevin J Torek

Timothy A Quick

Howard Kirsch

Kevin R Shea

Hongbin Zhu

Charles H Dennison

Yongjun Jeff Hu

Kevin G Donohoe

Everett Allen McTeer

Viju K Mathews

Guy F Hudson

Meet the Biggest South Asian Inventor in the World: Dr. Gurtej Sandhu

A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

Methods of forming nanostructures utilizing self-assembled nucleic acids

The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.

Method of forming photonics structures

A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

String driver assemblies including two-dimensional materials, and related memory devices

Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Epitaxial single crystalline silicon growth for a horizontal access device

A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Driver placement in memories having stacked memory arrays

A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Memory circuitry comprising a vertical string of memory cells and a conductive via and method used in forming a vertical string of memory cells and a conductive via

A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attractor species having at least one trap site and a chemical affinity for the diffusive species. The diffusive species is transferred from the precursor magnetic material to the precursor trap material where it bonds to the at least one attractor species at the trap sites. The species of the enriched trap material may intermix such that the enriched trap material becomes or stays amorphous. The depleted magnetic material may then be crystallized through propagation from a neighboring crystalline material without interference from the amorphous, enriched trap material. This enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.

Methods of forming electronic devices

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure. The free region is disposed between two nonmagnetic regions, which may both be configured to induce surface/interface magnetic anisotropy. The structure is therefore configured to have a high magnetic anisotropy strength, a high energy barrier ratio, high tunnel magnetoresistance, a low programming current, low cell-to-cell electrical resistance variation, and low cell-to-cell variation in magnetic properties. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Electronic devices including a seed region and magnetic regions

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.

Methods of forming nanostructures using self-assembled nucleic acids, and nanostructures therof

Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Methods of forming material within openings extending into a semiconductor construction, and semiconductor constructions having fluorocarbon material

A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

Transistors comprising two-dimensional materials and related memory cells and electronic devices

Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

Confined cell structures and methods of forming confined cell structures

Microelectronic devices including two-dimensional materials, and related memory devices and electronic systems

A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

Methods for inhibiting line bending during conductive material deposition, and related apparatus

Growing community of inventors

Boise, ID, United States of America

Gurtej S Sandhu