Micron Technology Incorporated

Gurpreet S Lugani

Kevin J Torek

Kevin R Shea

David A Kewley

Farrell Martin Good

Dave Pratt

Robert K Grubbs

Kyle B Campbell

Raju Ahmed

Frank Speetjens

Yung-Ta Sung

Mario J Di Cino

Aaron W Freese

Alex Kogan

Dan B Millward

Christopher W Petz

Matthew N Rocklein

Sanjeev Sapra

Ranjan Khurana

Devesh Dadhich Shreeram

Paul A Paduano

Sanket S Kelkar

Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

Conductive interconnects and methods of forming conductive interconnects

Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.

Protective sealant for chalcogenide material and methods for forming the same

A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating. After the removing, the pattern-interrupting second feature in the lower substrate material is used as a reference location to reckon which of the two different composition masking materials was used to make first spaces between the first features in an analysis area in the material that was above the lower substrate material or which of the two different composition masking materials was used to make second spaces between the first features in the analysis area that alternate with the first spaces. Structure independent of method is disclosed.

Integrated circuit, construction of integrated circuitry, and method of forming an array

Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.

Storage node shaping

A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Methods of forming capacitors

A method of forming a semiconductor device structure comprises forming a template material over a substrate, the template material exhibiting preferential wetting to a polymer block of a block copolymer. A positive tone photoresist material is formed over the template material. The positive tone photoresist material is exposed to radiation to form photoexposed regions and non-photoexposed regions of the positive tone photoresist material. The non-photoexposed regions of the positive tone photoresist material are removed with a negative tone developer to form a pattern of photoresist features. The pattern of photoresist features and unprotected portions of the template material are exposed to an oxidizing plasma to form trimmed photoresist features and a pattern of template features. The trimmed photoresist features are removed with a positive tone developer. Other methods of forming a semiconductor device structure, and a semiconductor device structure are also described.

Methods of forming semiconductor device structures, and related semiconductor device structures

Growing community of inventors

Boise, ID, United States of America

Gurpreet S Lugani