Mosaid Technologies Corporation

Semtech Canada Corporation

Conversant Intellectual Property Management Incorporated

Gurpreet S Bhullar

Graham A Allan

Ki-Jun Lee

Michael B Vladescu

A circuit is disclosed having a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal.

Device having non-linear filter

Non-linear filter for DML

A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

Process, voltage, temperature independent switched delay compensation scheme

An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.

Dual control analog delay element

A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Dual control analog delay element and related delay method

A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

An address counter cell for use in burst mode operation in a synchronous DRAM is described which, in response to a falling edge of a system clock, simultaneously loads address inputs into an external address master latch and an internal address master latch, and further enables a multiplexer to select between the external and internal address inputs. In response to a subsequent rising edge of the system clock, the selected address input is then loaded into a low-output-load capacitance slave latch and is further provided to complementary output nodes. The signal from one of the output nodes is also fedback to circuitry for incrementing the selected address internally for subsequent clock cycles remaining in the burst mode operation. Once the initial address of the burst operation has thusly been entered, for the remainder of the burst mode, the multiplexer selects the address loaded into the internal address master latch and operates as an edge-triggered flip/flop with the master latch accepting an incremented address in response to the falling edge of the system clock and with the slave latch loading and outputting the incremented address in response to the rising edge of the system clock. During a standby mode, circuitry is provided for disabling the counter cell and ensuring that the output nodes are stable and disabled.

Address counter cell

A regulator circuit is provided for use with cell plate voltage generators of memory cell capacitors and precharge bit lines voltage generators in semiconductor memories. The circuit employs a current source coupled to the charging reference voltage whose output is controlled by a level detector, which receives as input a reference level signal and the cell plate voltage. When the cell plate voltage drops below the reference level, the level detector triggers the current source, thereby recovering the cell plate voltage to the reference level. The level detector can be disabled through an input.

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Ottawa, Canada

Gurpreet S Bhullar