Apple Inc.

Gurjeet S Saund

Deniz Balkan

Munetoshi Fukami

Harshavardhan Kaushikkar

Kevin C Wong

Manu Gulati

Sukalpa Biswas

Erik P Machnicki

Guy Cote

James B Keller

Jim Chen Chou

Avi Bar-Zeev

Hao Pan

Sheng Zhang

Shane J Keil

Geoffrey Grant Stahl

Arthur Yasheng Zhang

Brian P Lilly

Ray Ling Chang

Timothy Robert Oriol

Tobias Eble

Justin A Hensley

Jason M Kassoff

Ling Su

Timothy John Millet

Michael G Frank

Arthur L Spence

Shinye Shiu

Ranjit Desai

Benjamin K Dodge

Venu Madhav Duggineni

Perry A Caro

Muditha Kanchana

Robert P Esser

Chaitanya Kosaraju

Erdem Guleyupoglu

James Han Wang

Peter F Holland

Brijesh Tripathi

Joseph P Bratt

Gerard Richard Williams

Aleksandr M Movshovich

Timothy R Paaske

Robert E Jeter

Wei-Han Lien

Shu-Yi Yu

Rakesh L Notani

Rohit Kumar Gupta

Neeraj Parik

Ben D Jarrett

Odutola Oluseye Ewedemi

Shailendra S Desai

Jim Jian Lin

Vijay Gupta

Seye Ewedemi

Alexsandr M Movshovich

A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.

Video pipeline

One implementation forms a composited stream of computer-generated reality (CGR) content using multiple data streams related to a CGR experience to facilitate recording or streaming. A media compositor obtains a first data stream of rendered frames and a second data stream of additional data. The rendered frame content (e.g., 3D models) represents real and virtual content rendered during a CGR experience at a plurality of instants in time. The additional data of the second data stream relates to the CGR experience, for example, relating to audio, audio sources, metadata identifying detected attributes of the CGR experience, image data, data from other devices involved in the CGR experience, etc. The media compositor forms a composited stream that aligns the rendered frame content with the additional data for the plurality of instants in time, for example, by forming time-stamped, n-dimensional datasets (e.g., images) corresponding to individual instants in time.

Media compositor for computer-generated reality

An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

Processor to memory with coherency bypass

One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

Method for chaining media processing

Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store data and a display control unit configured to retrieve data from the data storage device. The data storage device may be placed in a reduced power state that results in increased latencies for accessing data within the device. The display control unit is configured to monitor an amount of data available for processing within the display control unit. In response to determining the amount of data has fallen to a threshold level, and in anticipation of a forthcoming data access request, the display control unit conveys an indication that prevents the data storage device from entering or remaining in the reduced power state. Subsequently, the display control unit conveys a request for data to the data storage device which will not be in the reduced power state.

Proactive power management for data storage devices to reduce access latency

A method and apparatus for selective calibrations of a memory subsystem is disclosed. The memory subsystem includes a memory and a memory controller. The memory controller is configured to periodically perform calibrations of a data strobe signal conveyed to the memory and a reference voltage used to distinguish between a logic 0 and a logic 1. The memory subsystem is also coupled to receive a clock signal (e.g., at the memory controller). If a pending change of frequency of the clock signal is indicated to the memory controller during performance of a periodic calibration, the reference voltage calibration may be aborted prior to or during the performance thereof, while the data strobe calibration may be completed.

Memory calibration abort

An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Interfacing dynamic hardware power managed blocks and software power managed blocks

Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Credit lookahead mechanism

Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

Synchronizing transactions for a single master over multiple busses

Systems and methods for translating cache hints between different protocols within a SoC. A requesting agent within the SoC generates a first cache hint for a transaction, and the first cache hint is compliant with a first protocol. The first cache hint can be set to a reserved encoding value as defined by the first protocol. Prior to the transaction being sent to the memory subsystem, the first cache hint is translated into a second cache hint. The memory subsystem recognizes cache hints which are compliant with a second protocol, and the second cache hint is compliant with the second protocol.

Translating cache hints

Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Power control for cache structures

Growing community of inventors

Saratoga, CA, United States of America

Gurjeet S Saund