Wisconsin Alumni Research Foundation

Other

Gurindar Singh Sohi

Gagan Gupta

Srinath Sridharan

Hongil Yoon

Andreas I Moshovos

Craig Buchanan Zilles

Todd M Austin

Matthew Allen

Shyam Murthy

Koushik Chakraborty

Avinash Sodani

Terani N Vijaykumar

Philip M Wells

Scott E Breach

Saisanthosh Balakrishnan

Dionisios N Pnevmatikatos

A computer architecture provides a pre-sending of memory blocks from a lower level memory hierarchy component to a higher level memory hierarchy component using a table linking a set of memory blocks holding instructions that are executed in different fragments of a program. The table is used to pre-send memory blocks to the higher level memory hierarchy component in anticipation of their use by a processor executing the program.

Computer system with instruction pre-sending

A system for parallel execution of program portions on different processors permits speculative execution of the program portions before a determination is made as to whether there is a data dependency between the portion and older but unexecuted portions. Before commitment of the program portions in a sequential execution order, data dependencies are resolved through a token system that tracks read access and write access to data elements accessed by the program portions.

Computer architecture for speculative parallel execution

Interrupt handling on a multiprocessor computer executing multiple computational operations in parallel is provided by establishing a total ordering of the multiple computational operations and defining an architectural state at the time of the interrupt as if the computational operations executed in the total ordering.

Precise-restartable parallel execution of programs

A computer architecture provides a memory cache that is accessed not by physical addresses but by virtual addresses directly from running processes. Ambiguities that can result from multiple virtual addresses mapping to a single physical address are handled by dynamically tracking synonyms and connecting a limited number of virtual synonyms mapping to the same physical address to a single key virtual address that is used exclusively for cache access.

Cache accessed using virtual addresses

A system and method of parallelizing programs employs runtime instructions to identify data accessed by program portions and to assign those program portions to particular processors based on potential overlap between the access data. Data dependence between different program portions may be identified and used to look for pending 'predicate' program portions that could create data dependencies and to postpone program portions that may be dependent while permitting parallel execution of other program portions.

System and method for selectively delaying execution of an operation based on a search for uncompleted predicate operations in processor-associated queues

A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens.

System and method providing run-time parallelization of computer software using data associated tokens

A computer cache system delays cache coherence invalidation messages related to cache lines of a common memory region to collect these messages into a combined message that can be transmitted more efficiently. This delay may be coordinated with a detection of whether the processor is executing a data-race free portion of the program so that the delay system may be used for a variety of types of programs which may have data-race and data-race free sections.

Computer cache system providing multi-line invalidation messages

A computer system and method are provided to assess a proper degree of parallelism in executing programs to obtain efficiency objectives, including but not limited to increases in processing speed or reduction in computational resource usage. This assessment of proper degree of parallelism may be used to actively moderate the requests for threads by application processes to control parallelism when those efficiency objectives would be furthered by this control.

Computer system and method for runtime control of parallelism in program execution

Execution of a computer program on a multiprocessor system is monitored to detect possible excess parallelism causing resource contention and the like and, in response, to controllably limit the number of processors applied to parallelize program components.

System and method for controlling excessive parallelism in multiprocessor systems

A method of dynamic parallelization in a multi-processor identifies potentially independent computational operations, such as functions and methods, with a serializer that assigns a computational operation to a serialization set and a processor based on assessment of the data that the computational operation will be accessing upon execution.

Assigning different serialization identifier to operations on different data set for execution in respective processor in multi-processor system

An over-provisioned multicore processor employs more cores than can simultaneously run within the power envelope of the processor, enabling advanced processor control techniques for more efficient workload execution, despite significantly decreasing the duty cycle of the active cores so that on average a full core or more may not be operating.

Over-provisioned multicore processor

Distant parallelization of sequential programs is obtained by making parallelization decisions at the boundaries between program methods (e.g., functions and sub-routines). Experimentation suggests that such a partitioning allows for large-scale parallelization without data flow conflicts.

Data flow execution of methods in sequential programs

Parallelization of a program is performed by creating a distilled version of the program having higher execution speed but with unverified execution. The distilled program is executed rapidly to create state snapshots of the program that may be forwarded to secondary processors for execution of the actual program in parallel with other secondary processors similarly allocated. Each state snapshot is verified as the task is executed on a secondary processor by the preceding processor. The degree of parallelization is limited only by the speed up of the distilled program.

Method and apparatus for parallel execution of computer software using a distilled program

A data dependence prediction technique is used to establish linkage between two instructions using data so that accessing the data from memory may be bypassed. Instead, the data retrieved in the first data using instruction is temporarily stored in a local register to be used by the second data using instruction. Parallel processing techniques of squashing are used in the event that the prediction is erroneous.

Electronic processor providing direct data transfer between linked data consuming instructions

The data cache features an improved mechanism for accessing data from the data memory array of a data cache, by generating a predicted address and using it to access the data cache array in parallel with the effective address computation. The logic circuitry consists of elements which are capable of performing a carry-free addition (logical or arithmetic) of a predetermined number of base register address bits with the same number of offset register address bits. Methods to generate and verify the predicted index are also provided.

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Madison, WI, United States of America

Gurindar Singh Sohi