Winbond Electronics Corporation

Windbond Electronics Corp.

Guoxing Li

Bingxue Shi

Methods and systems of the present invention may be used to recognize digital image data arranged in rows and columns. Exemplary embodiments may include a feature extractor for extracting feature information from data representing the rows and columns of the digital image data, a feature compressor for compressing the extracted feature information, and a neural network for classifying the digital image data from the compressed, extracted feature information.

Unconstrained handwriting recognition

A handwriting recognition device using fuzzy logic and cellular neural network for unconstrained handwritten numeral classification is provided. The current mode VLSI classifier has a I/O circuit for inputting and outputting a plurality of membership functions. An extraction unit comprising a CCD extractor with a CNN structure and a compression unit receives a to-be-recognized character having a plurality of input features for generating a plurality of features values after compression. A membership function generator stores the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type membership degrees. A plurality of switched-current integrators receives the plurality of current-type membership degrees for generating a plurality of synthesis membership degrees. A k-WTA circuit is provided for comparing the plurality of synthesis membership degrees and output the plurality of synthesis membership degrees as well as the corresponding characters in an order of magnitude.

VLSI neural fuzzy classifier for handwriting recognition

A neural fuzzy data classifier for handwritten character classification is provided. The classifier has an I/O circuit for inputting and outputting a plurality of membership functions. An input buffer receives a to-be-recognized character having a plurality of input features for generating a plurality of features values. A main computation unit comprising a computation array and a local thresholds block store the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type weights. A difference circuit block compares the current output from the computation array and local thresholds lock. A plurality of switched-current integrators receives the plurality of current-type weights for generating a plurality of synthesis weights. A k-WTA circuit outputs the plurality of synthesis weights as well as the corresponding characters in an order of magnitude and the 10 current threshold block compares the plurality of synthesis weights and output a digital voltage.

Current-mode digital programmable neural fuzzy classifier

A circuit for extracting a connected component feature from an input image includes an input stage, a counting stage, a bit-preparing stage, and a bit-output stage. The input stage receives a bit pattern and detects a connected component in the bit pattern. The counting stage counts the number of connected components detected in the input stage and generates a current representing that number. The bit-preparing stage generates more than one current as a basis for information including more than one bit, based on the current generated in the counting stage, so that the information uniquely represents the number of connected components. The bit-output stage converts the currents generated in the bit-preparing stage into a digital output corresponding to the information.

Circuit for extracting connected component features from an image

A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that is indicative of a level of the second input signal. The comparing section is coupled with the input section and compares the first output signal and the second output signal to responsively generate a result. The comparing section includes a first comparing unit and a second comparing unit. The control section is coupled with the input section and the comparing section. Furthermore, the control section activates, when receiving an initial load signal, the first input unit, the second input unit, the first comparing unit, and the second comparing unit. Moreover, the control section deactivates, before receiving a second load signal, at least one of the first input unit and the first comparing unit when the first output signal is greater than the second output signal. In addition, the result generated by the comparing section is indicative of a level of the first output signal.

Signal sorting device and method

A k-WTA circuit for selecting inputs which have a maximum-magnitude and outputting the results. k-WTA is very useful in pattern classification such as k-nearest neighbor classifier, Hamming neural classifier and some cascaded classification systems, since one classifier can not achieve very high performance, however, if a small set of candidates can be provided, for example k(k<<N), then a simple classifier with small complementary feature sets can be cascaded to realize multi-stage classification. A k-WTA network is necessary to implement this function. The circuit as disclosed in the invention provides a design for a circuit in which the number of inputs with maximum magnitudes at any one time can be chosen. The circuit can have a plurality of inputs each of which has a corresponding output. In one embodiment of the invention external inputs can select the number of maximum-magnitudes inputs to be selected through the use of a current positive feedback loop. Depending on the number of maximum-magnitude inputs selected the circuit will output voltage levels on the outputs that correspond to inputs whose current levels have higher magnitudes when compared to other inputs. The circuit has the further advantages of reconfigurability, self-adaptivity, low complexity, high accuracy, expandability, and a large dynamic range.

Selectability of maximum magnitudes for K-winner take all circuit

A winner-take-all (WTA) circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal, to assist in the decision criteria of a winner-take-all network. The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current and a voltage level is outputted. The reference current is adjustable, and the invention also provides a WTA circuit with weighted inputs, and the ability to select between a 1-WTA, and a 2-WTA configuration. The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal.

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Beijing, China

Guoxing Li