Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Guowen Wei

Tom W Kwan

Xinyu Yu

Iuri Mehr

Fang Lin

Feng Su

Michael Inerfield

Yue Hu

A circuit includes a driver to provide a voltage at a node of a load and a first circuit to facilitate determining a load current at the node. The load is a capacitive load and the first circuit facilitates determining the load current by measuring a replica current and determining a capacitance of the load using values of the voltage and the replica current.

Panel impedance sensing via driver replica current

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

Method and apparatus for excess loop delay compensation in continuous-time sigma-delta analog-to-digital converters

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San Jose, CA, United States of America

Guowen Wei