Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Guowei Zhang

Purakh Raj Verma

Yisuo Li

Sanford Chu

Jeoung Mo Koo

Baofu Zhu

Zhiqing Li

Verma Purakh

Shyue Seng Tan

Danny Pak-Chum Shum

Yung Fu Chong

Jae Gon Lee

Shao-fu Sanford Chu

Zhao Lun

Chew Hoe Ang

Dong Kyun Sohn

Liang-Choo Hsia

Yun Ling Tan

Ming Li

Ee Jan Khor

Francis YongWee Poh

Pengfei Guo

Deyan Chen

Kah Wee Ang

Cho Khon

Chin Leng Ko

Yong Wah See

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a gate laterally positioned between the trench and the source, and a field plate inside the trench. The field plate is laterally positioned between the gate and the drain. The structure further comprises a gate dielectric between the gate and the semiconductor substrate. The gate dielectric includes a first section adjacent to the field plate and a second section adjacent to the source. The first section is thicker than the second section.

Laterally-diffused metal-oxide-semiconductor devices with a field plate

The present disclosure generally relates to trench isolation structures for semiconductor devices. More particularly, the present disclosure relates to semiconductor devices having trench isolation structures with varying depths for electrically isolating integrated circuit (IC) components in the semiconductor devices. The present disclosure also relates to method of forming the trench isolation structures.

Trench isolation structures with varying depths and method of forming the same

A device which includes a substrate having a device region is provided. The device region may be a high voltage device region. A source region and a drain region are disposed in the substrate within the device region. A gate is arranged over the substrate and between the source region and the drain region. A trench structure having a trench is disposed in the substrate within the device region. The trench structure is arranged on a first side of the gate where a predetermined distance is arranged between the trench structure and the first side of the gate. A well tap region is disposed adjacent to the source region. The well tap region is arranged at least around a bottom and a sidewall of the trench. The well tap region has a deeper depth within the substrate as compared to the source region.

High voltage devices and methods of forming the same

Laterally-diffused-metal-oxide-silicon (LDMOS) devices, integrated circuits including LDMOS devices, and methods for fabricating the same are provided. An exemplary LDMOS device includes a substrate having a surface, a gate structure overlying the surface and a channel region in the substrate below the gate structure, and a drain region in the substrate. The LDMOS device further includes a surface insulator region disposed between the gate structure and the drain region at the surface of the substrate and a dielectric block different from the surface insulator region and located over the surface insulator region. Also, the LDMOS device includes a field effect structure. The field effect structure includes a field plate disposed over and distanced from the surface of the substrate. The field effect structure also includes a conductive structure coupled to the field plate and extending from the field plate toward the dielectric block.

LDMOS devices, integrated circuits including LDMSO devices, and methods for fabricating the same

The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused MOSFET (LDMOS) and methods of manufacture. The structure includes: a gate structure having a drain region and a source region; and an oxidation extending from the gate structure to the drain region of the gate structure, the oxidation comprising a thinner oxide portion and a thicker oxide portion.

Laterally diffused mosfet with locos dot

A high voltage device may include a substrate, source and drain regions, a gate structure and an oxide layer. The substrate may include a recessed region with a recessed surface lower than a top surface of the substrate. The source and drain regions may be at least partially arranged within the substrate under the recessed surface and top surface respectively. The drain region may be positioned higher than the source region. The gate structure may include first and second portions arranged over the recessed region. The first and second portions may be nearer to the source and drain regions respectively. The oxide layer may include a first part between the first portion of the gate structure and the recessed surface, and a second part between the second portion of the gate structure and the recessed surface. The second part of the oxide layer may be thicker than the first part.

High voltage device and a method for forming the high voltage device

A high voltage (HV) transistor is integrated on a silicon-on-insulator (SOI) substrate. The HV transistor is disposed in a HV device region disposed on a bulk substrate of the SOI substrate. The HV device region includes a top field oxide which includes at least a part of a buried oxide (BOX) of the SOI substrate. A HV gate is disposed in HV region overlapping the HV top field oxide and includes first and second HV gate sidewalls. A drain is disposed on the bulk substrate and displaced from the first HV gate sidewall by the HV top field oxide. A source is disposed on the bulk substrate adjacent to the side of the second HV gate sidewall.

Extended drain transistor on a crystalline-on-insulator substrate

High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

[object Object]

Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a gate overlying the substrate. A drain is defined within the substrate, where the drain and the gate are separated by a drain distance. A source is defined within the substrate adjacent to the gate, wherein the source is divided into two or more source sections.

Integrated circuits with high voltage transistors and methods for producing the same

High voltage devices and methods for forming thereof are disclosed. A high voltage device includes a substrate having a device region, where the device region includes a source region and a drain region defined thereon. A transistor is disposed on the device region. The transistor includes a gate disposed over the substrate and in between the source and drain regions. First and second device wells are disposed in the substrate within the device region. The first device well is adjacent to a second side of the gate and the second device well is adjacent to a first side of the gate. Isolation regions are disposed within the substrate. The isolation regions include a device isolation region surrounding the device region and one or more isolation fingers disposed in a first portion of the device region adjacent to the first side of the gate.

High voltage device with low Rdson

A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The device also includes an n-well region surrounded by the p-type region, wherein the n-well is formed from an n-type epitaxial layer and the p-type region is formed by counter-doping the same n-type epitaxial layer.

Semiconductor device including an n-well structure

Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate. A floating gate is disposed over a transistor well. A control gate disposed over a control well is coupled to the floating gate. The control gate includes a control capacitor. A non-self-aligned source/drain (S/D) region is disposed within the transistor well and serves as an erase terminal.

Simple and cost-free MTP structure

A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions.

High gain device

Device and methods for forming a device are presented. The method includes providing a substrate. The substrate includes a resistor region defined by a resistor isolation region. A resistor gate is formed on the resistor isolation region. An implant mask with an opening exposing the resistor region is formed. Resistor well dopants are implanted to form a resistor well in the substrate. The resistor well is disposed in the substrate below the resistor isolation region. Resistor dopants are implanted into the resistor gate to define the sheet resistance of the resistor gate. Terminal dopants are implanted to form first and second resistor terminals at sides of the resistor gate. A central portion of the resistor gate sandwiched by the resistor terminals serves as a resistive portion.

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Singapore, Singapore

Guowei Zhang