Spansion Llc.

Advanced Micro Devices Corporation

Other

Integrated Silicon Solution Incorporated

Fujitsu Corporation

Guowei Wang

Nian Niles Yang

Aaron Lee

Nancy S Leong

Yonggang Wu

Sachit Chandra

Darlene G Hamilton

Yi He

Zhizheng Liu

Ming Sang Kwan

Xuguang Alan Wang

Sung-Yong Chung

Sung-Chul Lee

Yugi Mizuguchi

Yasushi Kasa

Fan Wan Lai

Tiao-Hua Kuo

Boon-Aik Ang

Hounien Chen

Sung Jin Yoo

Takao Akaogi

Johnny C Chen

Binh Quang Le

Michael A VanBuskirk

Johnny Chung-Lee Chen

Hongtau Mu

A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases below a reference current level.

Auto low current programming method without verify

A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Controlling AC disturbance while programming

A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Flash memory programming power reduction

Techniques for programming a non-volatile memory device, such as a Flash memory, include floating source lines of memory cells based on a data pattern that is being programmed to the memory device. The source lines to float are selected such that a distance between drain bit lines and source bit lines of different memory cells in a row is maximized. In this manner, leakage current between these drain bit lines and source bit lines can be decreased.

Flash memory programming with data dependent control of source lines

A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

Bitcell current sense device and method thereof

A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells () of a semiconductor memory device (). A high voltage generator () during program or erase operations provides a continuous high voltage level () on selected word lines () and maintains a continuous high voltage level supply to a bit line decoder () which sequentially provides the high voltage level () to a first portion of bit lines () and discharges () those bit lines () before providing the high voltage level to a second portion (). For additional improvements to program operations, the high voltage generator () decouples high voltages provided to the word lines () and the bit lines () by providing a current flow control device () therebetween and provides a boosting voltage at a time () to overcome a voltage level drop () resulting from a capacitor load associated with selected bit lines () and/or the bit line decoder () precharges () a second portion of the bit lines () while providing a high voltage level to a first portion to program () a first portion of memory cells (). For improvements to read operations, whether dynamic reference cells () are blank is determined by providing non-identically regulated high voltage levels from a first voltage source () to the dynamic reference cells () and from a second voltage source () to static reference cells () and, if the dynamic reference cells () are not blank, reads selected memory cells () by providing identically regulated high voltage levels to the selected memory cells (), the dynamic reference cells () and the static reference cells ().

Method and apparatus for high voltage operation for a high performance semiconductor memory device

A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Flash memory device having improved program rate

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

High performance flash memory device capable of high density data storage

A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before activating the operational-amplifier section. The capacitor is configured to store charge to supplement current being supplied from the operational-amplifier section. The voltage regulator may be used to supply power to non-volatile memory cells.

Voltage regulator with less overshoot and faster settling time

Growing community of inventors

San Jose, CA, United States of America

Guowei Wang