Intel Corporation

Huawei Technologies Co., Limited

Guotao Wang

Sairam Agraharam

Robert L Sankman

Thomas J De Bonis

Shengquan Ou

Todd Spencer

Yang Sun

Omkar G Karhade

Nitin A Deshpande

Eric Jin Li

Huiyang Fei

Jiangqi He

Sudarshan V Rangaraj

Tae Hong Kim

Andrew Yeohi

An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Multi-chip packaging

A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.

Embedded thin-film magnetic inductor design for integrated voltage regulator (IVR) applications

Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

Warpage control for microelectronics packages

Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.

Methods of forming stepped bumps and structures formed thereby

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Chandler, AZ, United States of America

Guotao Wang