Boe Technology Group Co., Ltd.

Ordos Yuansheng Optoelectronics Co., Ltd.

Beijing Timeriver Technology Co., Ltd.

Guoqing Zhang

Xiaowei Wang

Hongxia Yang

Weifeng Wang

Pucha Zhao

Hongwei Gao

Ke Zhao

Xiaopeng Bai

Haotian Chen

Yan Zong

Zhixin Guo

Longfei Yang

Meili Guo

Feiwen Tian

Yanbin Dang

Zhihui Jia

Lei Wang

Ming Wang

Yu Fu

Yaorong Liu

Xingliang Wang

Xuepeng Ji

Yi Qu

Liang Sun

Jie Wu

Shanshan Bao

Xinxin Jin

Yuebai Han

Hailong Liu

Tuan Liang

Huayang Xu

Yanyu Liu

Zhigang Sun

Chenwei Wang

Chaoqiong Guo

Luchang Ren

Zhangjun Song

A substrate, a panel, a detection device and an alignment detection method are provided. The substrate includes first signal connection pins arranged in parallel side by side and at least one first alignment detection pin, wherein the at least one first alignment detection pin is located on at least one side of the first signal connection pins in an arrangement direction of the first signal connection pins, and arranged in parallel with the first signal connection pins.

Substrate, panel, detection device and alignment detection method

A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.

Test circuitry and method for testing the same, test system

The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.

Method and system for aging process on transistors in a display panel

The present disclosure belongs to the field of display technology, and particularly relates to a test circuit, a display substrate, a test method of a display substrate and a display apparatus. The test circuit includes a signal generating device and a plurality of output channels that are mutually independent. Each output channel includes a signal line configured to transmit a test signal. The signal generating device is coupled to the plurality of output channels, and is configured to provide, to each of at least one of the plurality of output channels, the test signal corresponding to an impedance of the signal line in the output channel, and provide the test signal to the signal line in the output channel.

Test circuit, display substrate, test method thereof and display apparatus

A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes: a voltage conducting layer, at least part of which is in a display area; a voltage connecting terminal in a peripheral circuit area, and a conductive lead in the peripheral circuit area. The conductive lead includes: a first annular portion, a second annular portion, and a plurality of bridging portions. The first annular portion is connected to the voltage conducting layer, the second annular portion surrounds the first annular portion and connected to the voltage connecting terminal, and a first end and a second end of each bridging portion are connected to the first annular portion and the second annular portion respectively.

Conductive lead arrangement for display substrate and manufacturing method thereof, and display device

A defect detection circuit and a defect detection method for a light-emitting element, a display driving device, a display device, and a defect detection method for the display device are provided. The defect detection circuit includes a power source signal adjustment sub-circuit, a data signal adjustment sub-circuit, a first initial signal adjustment sub-circuit, a second initial signal adjustment sub-circuit and a storage capacitor connected to a control end of a driving transistor. The storage capacitor is configured to control the driving transistor to be turned off under the effect of a power source signal, a data signal and an initial signal, to enable the second initial signal adjustment sub-circuit to apply the initial signal to a light-emitting sub-circuit, thereby to enable the light-emitting sub-circuit to emit light. The display driving device includes the defect detection circuit.

Defect detection circuit and method for light-emitting element, display driving device, display device and defect detection method thereof

A display substrate includes: a display driving signal line; and at least one set of testing pads, wherein each set of the testing pads includes: a plurality of light-on testing pads arranged successively and connected to the display driving signal line; and two pin-miss testing pads electrically connected to one another while not connected to the display driving signal line.

Display substrate, light-on device and method for testing alignment of light-on testing pin

A detecting apparatus and method, repairing apparatus and method, and repairing system of AMOLED display device are provided. The detecting apparatus includes: an illuminating device for sequentially illuminating a plurality of detection regions of a screen of the AMOLED display device, the screen being divided into the plurality of detection regions, each of the detection regions including at least one light-emitting unit; a current detecting device for acquiring a detection current which is a sum of driving currents of the light-emitting unit in the detection region being illuminated; and a judging device for judging whether the detection region corresponding to the detection current is a defective region according to the detection current. The apparatus can detect luminance uniformity of the AMOLED display device. The detection efficiency is high, the detection standard is unified and the detection accuracy is high.

Detecting apparatus and method, repairing apparatus and method, and repairing system of AMOLED display device

A set of measurement voltages having different voltage values are subsequently inputted to a measurement voltage input terminal of the pixel driving circuit, a light emitting state of a light emitting device under each measurement voltage is detected, and it is determined whether a storage capacitor in the pixel driving circuit is normal based on the light emitting state of the light emitting device.

Capacitor detection method and pixel driving circuit

The present disclosure relates to a power supply device for a display panel, a manufacturing method, a power supplying method, and a display device. The power supply device may include: a first line surrounding the display panel and electrically connected to sub-pixels of the display panel; at least one first power supply terminal disposed at a first side of the display panel and connected to a first line segment of the first line located at the first side of the display panel; at least one second power supply terminal connected to a second line segment of the first line located at a second side of the display panel to compensate for a voltage drop of the first power supply terminal on the first line. The first side and the second side of the display panel are opposite sides of the display panel.

Power supply device for display panel, manufacturing method, power supplying method and display device

The present disclosure provides a signal loading method and a signal generator. The signal loading method includes: loading a first pair of voltage signals to at least one pair of separate signal channels for a time period, respectively, wherein the first pair of voltage signals have a first voltage difference therebetween; and determining whether a short circuit occurs in the at least one pair of signal channels within the time period, and if it is determined that no short circuit occurs in the at least one pair of signal channels within the time period, loading a second pair of voltage signals having a second voltage difference therebetween to the at least one pair of signal channels at the end of the time period. The second voltage difference is greater than the first voltage difference.

Signal loading method and signal generator

The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I&#x3c;IT&#x2264;IF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.

Circuit board and method for manufacturing the same, terminal test device

The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A&#x2212;40) to (A&#x2212;8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A&#x2212;80) to (A&#x2212;16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd&#x2212;Vs&#x3c;0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.

Method for electrically aging a PMOS thin film transistor

Growing community of inventors

Beijing, China

Guoqing Zhang