Qualcomm Incorporated

Guoqing Miao

Ankit Srivastava

Seyfollah Seyfollahi Bazarjani

Peter J Shah

Mustafa Keskin

Sameer Wadhwa

Jeffrey Mark Hinrichs

Xiaohong Quan

Joseph Robert Fitzgerald

Eugene Robert Worley

Prajakt Kulkarni

Shahin Mehdizad Taleie

Hui-Ya Liao Nelson

Seyed Arash Mirhaj

Arash Mehrabi

Justin Joseph Rosen Gagne

Gene Hyde McAllister

Derick Hugunin

Jan Paul Van Der Wagt

Khalid Junaid Sidiqi

Gerrit Groenewold

Eunyung Sung

Uma Chilakapati

William C Scofield

Seyfi Bazarjani

Matt Sienko

Thurman S Deyerle, Iv

Joseph R Fitzgerald

Prajakt V Kulkarni

Gene H Mcallister

Khalid J Sidiqi

Joseph Fitzgerald

A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

Charge-pump-based current-mode neuron for machine learning

A processor-implemented method for managing bus traffic of a system-on-a-chip (SoC) includes receiving a mixed signal in a computing device including the SoC. One or more polarity changes of a slope of a waveform corresponding to the mixed signal are detected. One or more of an analog-to-digital converter (ADC) or a portion of SoC bus traffic related to ADC operation are selectively disabled between one or more polarity changes in the slope of the waveform.

Waveform-aware mixed signal measurement system for bus traffic reduction in system-on-a-chip devices

Methods and apparatus for supplying power to a dynamic load, such as a neural network circuit. One example power supply circuit generally includes a voltage regulator circuit and a distribution circuit coupled to one or more outputs of the voltage regulator circuit. The distribution circuit is configured to output different amounts of current based on changes in the dynamic load. For certain aspects, the dynamic load includes a neural network circuit having a plurality of segments. In this case, the distribution circuit may be configured to output the different amounts of current based on which segment in the plurality of segments of the neural network circuit is active.

Neural-network-based power management for neural network loads

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

Low-power compute-in-memory bitcell

A system and method of improving the efficiency in the power consumption of an audio system. In essence, the technique is to adjust the power delivered from the power supply to the analog section, such as the power amplifier, in response to the volume level indicated by the volume control module and/or in response to the detected characteristic of the input audio signal. Thus, in this manner, the analog section is operated in a manner that is related to the level of the signal it is processing. Additionally, the system and method also relate to a technique of adjusting the dynamic ranges of the digital signal and the analog signal to improve the overall dynamic range of the system without needing to consume additional power.

System and method of reducing power consumption for audio playback

Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Switch techniques for load sensing

An audio system that reduces or eliminates click and pop noise during power up and power down operations. In particular, the audio system includes an amplifier with an input adapted to receive an input audio signal and an output adapted to produce an amplified output audio signal for an associated speaker. The audio system further includes a noise reduction circuit adapted to smoothly apply and remove a DC voltage to and from the output of the amplifier in a manner that reduces or eliminates click and pop noise from being generated by the associated speaker. The DC voltage at the output of the amplifier may be derived from a DC reference voltage source and/or from the input audio signal.

System and method of reducing click and pop noise in audio playback devices

Techniques for utilizing a plurality of switches to reduce crosstalk in a headset jack for accommodating both European and North American type headset plugs. In an aspect, a six-switch solution is provided to selectively couple first and second terminals of the jack to a ground and a microphone terminal, and further to selectively couple a ground sensing input to the first or second terminal of the jack. The ground sensing input is provided to left and right audio channel amplifiers for driving the corresponding left and right terminals of the headset, to provide a common-mode reference level to the left and right audio channel amplifiers. In another aspect, at least four physical pins are provided to couple the switches to the ground and microphone terminals of the jack, and the connections between the ground sensing inputs and the jack may be provided adjacent to the jack for better isolation.

Headset switches with crosstalk reduction

Techniques for designing a transconductor configurable to have a low transconductance. In one aspect, a voltage to current conversion module is coupled to a 1:N current replication module. The voltage to current conversion module may be implemented as an operational amplifier configured with negative feedback to generate a current through a transistor, wherein such current is proportional to the difference between an input voltage and a common-mode reference. The 1:N current replication module is configured to mirror the generated current in another transistor, to a predetermined ratio, such that the output current is also proportional to the difference between the input voltage and the common-mode reference. In exemplary embodiments, the output stage driving the output current may be configured to operate as a Class A, Class B, or Class AB type amplifier.

Low GM transconductor

Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Adaptive gain adjustment system

A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Switched-capacitor DC blocking amplifier

Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

Charge pump electrostatic discharge protection

A digital offset is combined with an audio signal in the digital domain to cancel an output offset caused by one or more analog components processing the same audio signal. In this manner, the offset at the output of the audio signal path (e.g., at a power amplifier output) is reduced or eliminated. Consequently, audible artifacts, such as click-and-pop artifacts, can be reduced or eliminated. In audio devices operating in ground-referenced capless mode, power consumption is reduced because of reduced or eliminated direct current (DC) leakage current through speakers or headsets of such audio devices. In some circumstances, the digital offset in the digital domain may be applied at substantially all times of operation of the audio signal path.

Suppressing output offset in an audio device

An improved power amplifier system is provided. The power amplifier system includes a programmable digital filter and a power amplifier, each responsive to a plurality of frequency response settings and switching frequency settings, respectively. Each frequency response setting and switching frequency setting is adaptively selected by a processor device to match a bandwidth of an incoming audio signal. The processor device identifies the current bandwidth of an incoming audio signal and adaptively selects a switching rate setting and a frequency response setting based on the current bandwidth. The frequency response setting is selected so as to reduce noise fold over in the power amplifier for a corresponding bandwidth, sampling rate setting, and switching frequency setting.

Digital filtering in a Class D amplifier system to reduce noise fold over

A method and an apparatus powers down an analog integrated circuit. A power down circuit is electrically coupled to the analog circuit and is adapted to power down the analog circuit in response to receiving a power down signal. A node protection circuit is electrically coupled to the analog circuit and is adapted to provide a predetermined voltage potential to at least one predetermined node in the analog circuit in response to receiving the power down signal when a voltage potential at the at least one predetermined node is not determined by the power down circuit.

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San Diego, CA, United States of America

Guoqing Miao