Micron Technology Incorporated

Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Guoqing Chen

Roger Lee

James Pan

Lee Chang

Mieno Fumitake

Fumitake Mieno

Bong Jae Lee

A liquid crystal on silicon (LCOS) device includes a semiconductor substrate, a metal-oxide semiconductor (MOS) device layer overlying the semiconductor substrate, a planarized interlayer dielectric layer overlying the MOS device layer, a plurality of recessed regions formed within a portion of the interlayer dielectric layer, a metal layer filling each of the recessed regions to form a plurality of respective electrode plates corresponding to each of the recessed regions. The LCOS device further includes a protective layer overlying a surface of each of the plurality of electrode plates, a liquid crystal film overlying the protective layer, and a mirror finish formed on each of the surface of the electrode plates for reflecting light. The mirror finish is substantially free from dishes and scratches from a chemical mechanical polishing process.

Method and structure for fabricating smooth mirrors for liquid crystal on silicon devices

An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first interlayer dielectric layer. A contact structure including metallization is within the first interlayer dielectric layer and a metal layer is coupled to the contact structure. A passivation layer is formed overlying the metal layer. Preferably, an air gap layer is coupled between the passivation layer and the metal layer, the air gap layer allowing a portion of the metal layer to be free standing. Depending upon the embodiment, a portion of the air gap layer may be filled with silicon bearing nanoparticles, which may be oxidized at low temperatures. This oxidized layer provides mechanical support and low k dielectric characteristics. Preferably, a portion of the air gap layer is filled with a low k dielectric material as well.

Method and structure for low-k interlayer dielectric layer

A dynamic random access memory device including a capacitor structure, e.g., trench, stack. The device includes a substrate (e.g., silicon, silicon on insulator, epitaxial silicon) having a surface region. The device includes an interlayer dielectric region overlying the surface region. In a preferred embodiment, the interlayer dielectric region has an upper surface and a lower surface. The device has a container structure within a portion of the interlayer dielectric region. The container structure extends from the upper surface to the lower surface. The container structure has a first width at the upper surface and a second width at the lower surface. The container structure has an inner region extending from the upper surface to the lower surface. In a specific embodiment, the container structure has a higher dopant concentration within a portion of the inner region within a vicinity of the lower surface and on a portion of the inner region near the vicinity of the lower surface. The device also has a doped polysilicon layer overlying the inner region of the trench structure. The device has a first hemispherical grained silicon material having a first grain dimension near the vicinity of the lower surface and a second hemispherical grained silicon material having a second grain dimension near a vicinity of the upper surface of the container structure. In a preferred embodiment, the first grain dimension has an average size of no greater than about &#xbd; of an average size of the second grain dimension to prevent any bridging of any portions of the hemispherical grained silicon material within the vicinity of the lower surface.

Method and structure for fabricating capacitor devices for integrated circuits

A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g., BPSG, FSG) overlying the transistor layer. The method includes planarizing the interlayer dielectric layer and forming a sacrificial layer (e.g., bottom antireflective coating, polymide, photoresist, polysilicon) overlying the planarized interlayer dielectric layer. The method includes forming a plurality of recessed regions within a portion of the interlayer dielectric layer through the sacrificial layer while other portions of the interlayer dielectric layer remain intact. Preferably, lithographic techniques are used for forming the recessed regions. The method includes forming an aluminum layer (or other reflective layer or multilayers) to fill the recessed regions and overlying remaining portions of the sacrificial layer and selectively removing the aluminum layer overlying portions of the sacrificial layer to form a plurality of electrode regions corresponding to each of the recessed regions.

Method and structure for low k interlayer dielectric layer

An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

Tilted array geometry for improved MRAM switching

The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Methods of forming hemispherical grained silicon on a template on a semiconductor work object

A method for forming bit line and storage node contacts for a dynamic random access device, e.g., DRAM. Other devices (e.g., Flash, EEPROM) may also be included. The method includes providing a substrate, which has a bit line region and a capacitor contact region. The method also includes forming at least a first gate structure and a second gate structure overlying the substrate. The first gate structure and the second gate structure include an overlying cap. The method also includes forming a conformal dielectric layer overlying the first gate structure, the second gate structure, the bit line region, and the capacitor contact region. The method includes forming an interlayer dielectric material overlying the conformal dielectric layer and planarizing the interlayer dielectric material. The method includes forming a masking layer overlying the planarized interlayer dielectric material and exposing a continuous common region within a portion of the planarized interlayer dielectric material overlying a portion of the first gate structure, a portion of the second gate structure, a portion of the bit line region, and a portion of the capacitor contact region. A first etching process is performed to remove the exposed portion of the planarized interlayer dielectric layer. A second etching process is performed to remove a portion of the conformal dielectric layer on the bit line region and to remove a portion of the conformal dielectric layer on the capacitor contact region while using other portions of the conformal layer as a mask to prevent a portion of the first gate structure and a portion of the second gate structure from being exposed. The method deposits a polysilicon fill material within the continuous common region and overlying the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to cover portions of the bit line region, the capacitor contact region, the first gate structure, and the second gate structure to a predetermined thickness. The method includes planarizing the polysilicon fill material to reduce the predetermined thickness and to simultaneously reduce a thickness of a portion of the interlayer dielectric material.

Method and resulting structure for fabricating DRAM cell structure using oxide line spacer

A method and device for manufacturing a mask ROM integrated circuit device to reduce influences of punch through between source and channel regions that output improper program readings. The method includes forming well regions using an implant process on semiconductor substrate and forming a plurality of buried implant regions through first patterned mask. The first patterned mask is formed overlying the semiconductor substrate. Each of the buried implant regions includes a source region and a drain region for each respective memory cell region. The memory cell region is one of a plurality of memory cell regions. The method also forms pocket regions adjacent to a vicinity of each of the buried implant regions within the channel region for each of the memory cell regions. A first pocket region is defined between the channel region and source region and a second pocket region is defined between the channel region and the drain region for each memory cell region. The method includes programming one or more selected channel regions using implantation to program respective one or more selected memory cell regions.

Mask-ROM process and device to prevent punch through using a halo implant process

Structures and methods for making a magnetic structure are discussed. Various embodiments increase a magnetic field to unambiguously select a magnetic memory cell structure. One method includes folding a current line into two portions around a magnetic memory cell structure. Each portion contributes its magnetic flux to increase the magnetic field to unambiguously select the magnetic memory cell structure. Another method increases the flux density by reducing a cross-sectional area of a portion of the current line, wherein the portion of the current line is adjacent to the to the magnetic memory cell structure.

Growing community of inventors

Shanghai, China

Guoqing Chen