Texas Instruments Corporation

Other

Agilent Technologies, Inc.

Texax Instruments Incorporated

Agilent Technologies Texas Instruments Incorporated

Avago Technologies General IP Pte, Ltd.

Guoqiang Xing

Scott Robert Summerfelt

Stephen Roy Gilbert

Theodore Sidney Moise

Luigi Colombo

Mark R Visokay

Francis Gabriel Celii

Shawming Ma

Ping Jiang

Justin F Gaynor

Wei-Yung Hsu

Hyesook Hong

Tomoyuki Sakoda

Rajesh B Khamankar

Robert Kraft

Patricia Beauregard Smith

Kenneth D Brennan

Changming Jin

Andrew McKerrow

David Brian Aldrich

Rahim Kavari

Sanjeev Aggarwal

Laura Wills Mirkarimi

Girish Anant Dixit

Abbas Ali

Mona M Eissa

Jun Amano

Somnath S Nag

Ted S Moise

Eden M Zielinski

Kenneth Joseph Newton

Mark A Kressley

Abha Rani Singh

Jeff A West

Karen H R Kirmse

Zhicheng Tang

Alvin L S Loke

Laura Wills-Mirkarimi

Glenn A Cerny

Rob Kraft

Andrew Ralston

Scott Summerfelt

Stephen R Gilbert

Theodore Moise

A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Integrated circuit and method

Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.

Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities

Damascene methods for forming copper conductors () are disclosed. According to the disclosed method, a dual cap layer () is formed over an organosilicate glass insulating layer () prior to the etching of a via or trench toward an underlying conductor (). The dual cap layer includes a layer of silicon carbide () and a layer of silicon nitride (). The silicon carbide layer () and silicon nitride layer () can be deposited in either order relative to one another. The silicon carbide layer () maintains the critical dimension of the via or trench as it is etched through the insulating layer (), while the silicon nitride layer () inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

Dual cap layer in damascene interconnection processes

An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layerof FIG.) over the substrate; forming a photoresist layer (layerof FIG.) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium. The gas which includes hydrogen or deuterium is, preferably, comprised of a gas selected from the group consisting of: NH, NH, HS, CH, and deuterated forms of these gases, and may, additionally, include a forming gas. The forming gas is, preferably, comprised of a gas consisting of: argon, nitrogen, and any other inert gas.

Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization

A dual damascene process flow for forming interconnect lines and vias in which at least part of the via () is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD () and IMD (). After the at least partial via etch, a BARC () is deposited over the structure including in the via (). Then, the trench () is patterned and etched. Although at least some of the BARC () material is removed during the trench etch, the bottom of the via () is protected.

Process flow for dual damescene interconnect structures

Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Ferroelectric capacitor plasma charging monitor

The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Post-etch cleaning treatment

A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch

Plasma treating a low-k dielectric layer ( ) using an oxidation reaction (e.g., O ) to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The plasma treatment is performed to either pretreat a low-k dielectric ( ) before forming the pattern ( ), during a rework of the pattern ( ), or between via and trench patterning to reduce resist poisoning.

Plasma treatment of low-k dielectric films to improve patterning

Treating a low-k dielectric layer ( ) using a highly oxidizing wet solution (e.g., H SO ) to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The wet treatment is performed to either pre-treat a low-k dielectric ( ) before forming the pattern ( ) or during a rework of the pattern ( ) to reduce resist poisoning.

Treatment of low-k dielectric films to enable patterning of deep submicron features

An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer of FIG. ) over the substrate; forming a photoresist layer (layer of FIG. ) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium. The gas which includes hydrogen or deuterium is, preferably, comprised of a gas selected from the group consisting of: NH , N H , H S, CH , and deuterated forms of these gases, and may, additionally, include a forming gas. The forming gas is, preferably, comprised of a gas consisting of: argon, nitrogen, and any other inert gas.

A carbon hardmask ( ) for etching hard-to-etch materials ( ) such as Pt, Ir, Ru, IrO , RuO , BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sputter etching using argon and limited or no oxygen may be used to etch the hard-to-etch materials ( ) with high selectivity to the carbon hardmask ( ).

Using a carbon film as an etch hardmask for hard-to-etch materials

A method for etching a feature in a platinum layer overlying a second material without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer between the platinum layer and the second material; forming a hardmask layer over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer , the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti&mdash;Al&mdash;N including at least 1% of aluminum.

Method for forming integrated circuit capacitor and memory

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Plano, TX, United States of America

Guoqiang Xing