Spreadtrum Communications (Shanghai) Co., Ltd.

Guoming Rao

Huimin Zhang

Kai Chen

Zhengfei Xiao

He Yang

Disclosed in the present invention are a processor micro-architecture, an SoC chip and a low-power-consumption intelligent device. The processor micro-architecture comprises a co-processor and at least two main processors, wherein each main processor is connected to the co-processor by means of a request processing unit; the request processing unit is used for determining, when a usage request that is initiated by the two main processors has been received, a processing sequence for the main processors that initiate the request, and generating and sending a feedback instruction to different main processors according to the processing sequence; and the main processor is used for sending a processing instruction to the co-processor for processing when the feedback instruction represents that usage is allowed. A plurality of main controllers access the same co-processor in a shared manner, thereby satisfying an instruction-level delay, and achieving the optimum balance between performance and power consumption.

Processor micro-architecture, SoC chip and low-power-consumption intelligent device

A wearable device and an image signal processing apparatus thereof are provided. The image signal processing apparatus comprises an image acquisition device, an image data processing module, and an application processor; the application processor is used for controlling, when detecting that the wearable device enables a shooting preview mode, the image data processing module to switch from a sleep state or a power-down state to a working state; the image acquisition device is used for acquiring original image data; the image data processing module is used for obtaining the original image data and processing the original image data.

Wearable device and image signal processing apparatus thereof

Disclosed are a system-on-chip and a method for managing a working mode thereof, and a smart wearable device. The method comprises the following steps: in a working mode, a master control subsystem controlling a functional subsystem to implement a corresponding function, and responding to interrupt signals of the functional subsystem and a secondary control subsystem; in a dormant mode, the secondary control subsystem responding to the interrupt signal of the functional subsystem, and the master control subsystem prohibiting responding to the interrupt signal of the functional subsystem; and in an ultra-low power consumption mode, the master subsystem being powered off, and the secondary control subsystem responding to the interrupt signal of the functional subsystem. In the present disclosure, on the premise of meeting a normal function requirement of the system-on-chip, the power consumption of the system-on-chip is reduced to the greatest possible extent.

Growing community of inventors

Shanghai, China

Guoming Rao