Yozan Corporation

Sharp Corporation

Guoliang Shu

Makoto Yamamoto

Weikang Yang

Wiwat Wongwarawipat

Sunao Takatori

A circuit for weighted addition which includes a transistor having a gate and a plurality of resistance elements. Each resistance element has a first and second end. The first end of each resistance element is impressed with a voltage, and the second end of each resistance element is connected to the gate of the transistor. The circuit is small in size and renders precise and various types of weighted addition possible.

Circuit for weighted addition

An analog calculation circuit has a circuit input for receiving a first input voltage, a circuit output, a first timer, and a second timer. The first timer has a first capacitive coupler, a first RC circuit, and a first threshold circuit for outputting a first timer output voltage. The first threshold circuit has a first threshold input terminal. The first capacitive coupler has a first capacitive coupler input connected to the circuit input, a second capacitive coupler input, and a first capacitive coupler output connected to the first threshold input terminal. The first RC circuit has a first resistance, a first capacitance, a first RC input for receiving a second input voltage, and a first RC output connected to the second capacitive coupler input. The second timer has a second RC circuit, a second threshold circuit for outputting a second timer output voltage to the second RC circuit, and for receiving the first timer output voltage. The second RC circuit has a second resistance, a second capacitance, a second RC input for receiving a third input voltage, and a second RC output connected to the circuit output. A third timer, similar in design to the first timer may also be used in the calculation circuit.

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Tokyo, Japan

Guoliang Shu