Pixelworks, Inc.

S3 Incorporated, Inc.

Guojin Liang

J Eric Ruetz

A multi-link receiving mechanism (MRM) is disclosed comprising a plurality of receivers. Each receiver receives a separate data stream, and all receivers receive the same clock signal. The data streams may arrive at the MRM out of alignment relative to each other (i.e. may have inter-pair skew), and the clock signal need not be aligned with any of the data streams. In response to the clock signal and the data stream, each receiver delays the clock signal by a variable delay to derive a reference signal. This is done to achieve a desired relative alignment between the data stream and the reference signal. Once the reference signal is derived, it is used by the receiver to generate a plurality of latching control signals. These latching control signals are thereafter used by the receiver to latch all of the data units of the data stream. Data from the data stream is thus recovered. Each of the receivers operates in the manner described to recover data from each of the data streams. Because each receiver individually adjusts for the varying alignments of the various data streams, the MRM is able to accommodate and properly process data streams with inter-pair skew.

Multi-link receiver and method for processing multiple data streams

An improved receiver architecture is disclosed comprising a latching mechanism coupled to receive a data stream, and a signal generator for generating latching control signals for controlling the operation of the latching mechanism. The signal generator generates one latching control signal per data period of the data stream, with each latching control signal coinciding approximately with the midpoint of a corresponding data period. The signal generator generates the latching control signals based upon a reference signal, which in one embodiment, coincides approximately with the midpoint of a data period of the data stream. The receiver may further comprise an adjustable delay element and a delay adjustment control. The adjustable delay element receives a clock signal and imposes a variable delay thereon to derive the reference signal used to generate the latching control signals. The magnitude of the variable delay is controlled by the delay adjustment control. In one embodiment, the variable delay is set such that the reference signal is made to coincide approximately with the midpoint of a data period of the data stream. With the ability to adjust the variable delay, the receiver is able to derive a proper reference signal regardless of the alignment of the data stream.

Receiver architecture

Multi-link receiver mechanism for processing multiple data streams

A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.

Growing community of inventors

Milpitas, CA, United States of America

Guojin Liang