Boe Technology Group Co., Ltd.

Beijing Boe Display Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Hefei Boe Display Technology Co., Ltd.

Guohuo Su

Zhihua Sun

Xu Zhang

Zhihao Zhang

Jiantao Liu

Yinlong Zhang

Weichao Ma

Ning Zhang

Shulin Yao

Baoyu Liu

Jituo Tang

Yanping Liao

Changcheng Liu

Senwang Li

Guangquan He

Jian Li

Hui Zhang

Song Liu

Yingmeng Miao

Yujie Gao

Wenkai Mu

Jianming Wang

Jianhua Huang

Wenpeng Ma

Ming Deng

Wenliang Liu

Jinling Zhang

Yanjiao Pan

Tianxun Xiu

Jing Ma

Zhun Lin

Yinshu Zhang

Xueliang Yang

A temperature control circuit of a driver chip, a temperature control method of the driver chip, a power management integrated chip, a timing control driver board and a display apparatus are disclosed. The temperature control circuit includes a switching transistor, a comparison circuit and a control circuit; a first electrode of the switching transistor is connected with a first node, a second comparison end and the first electrode or a second electrode of the switching transistor are connected to a second node; the control circuit is configured to output a first reference voltage to the comparison circuit, the comparison circuit is configured to compare a magnitude relationship between a voltage on the second comparison end and the first reference voltage and output a comparison result; the control circuit acquires the comparison result and determines whether an output current on the boost circuit is excessively large.

Temperature control circuit and temperature control method of driver chip and timing control driver board

A source driving circuit includes: a logic and control sub-circuit configured to convert a source data signal into a data signal; a latch sub-circuit configured to, receive the data signal, latch an odd-numbered row of data in an odd-numbered frame, and latch an even-numbered row of data in an even-numbered frame; and an output sub-circuit configured to: receive the odd-numbered row of data in the odd-numbered frame and output the odd-numbered row of data in a first set duration, which is greater than a charging time of sub-pixels in the even-numbered row and less than or equal to twice the charging time; and receive the even-numbered row of data in the even-numbered frame and output the even-numbered row of data in a second set duration, which is greater than a charging time of sub-pixels in the odd-numbered row and less than or equal to twice the charging time.

Source driving circuit, source driving method, display device and display driving method

A method for debugging the display panel includes: acquiring a target correction data table of the display panel in each of at least one color mode by debugging the display panel in each of the at least one color mode. Debugging the display panel in each of the at least one color mode includes: controlling the display panel to display a test picture in the color mode; acquiring an initial display parameter curve based on a display parameter of the test picture; determining a reference display parameter curve based on the initial display parameter curve and a standard display parameter curve; and determining the target correction data table based on the reference display parameter curve and the standard display parameter curve.

Method, apparatus and system for debugging display panel

The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.

Timing controller board, main control board, display device, and detection method thereof

A heat dissipation structure and a manufacturing method thereof and a display device. The heat dissipation structure includes: a heat dissipation plate body, including an evaporation part and a condensation part; a plurality of micro-cavity structures, disposed in the heat dissipation plate body, two ports of each of the micro-cavity structures being sealed, and the micro-cavity structures being filled with liquid. Each of the micro-cavity structures extends from the evaporation part to the condensation part, and after the liquid absorbs heat at the evaporation part to change into vapor, the vapor moves toward the condensation part, and the vapor moved to the condensation part is condensed and liquefied and moves toward the evaporation part to achieve heat dissipation.

Heat dissipation structure for chip-on-film, manufacturing method thereof, and display device

The present disclosure relates to the field of display technology and, in particular, to a pixel charging method, a pixel charging circuit, a display device, and a display control method. The pixel charging method includes acquiring a state of a backlight source and adjusting a charging time of a sub-pixel corresponding to the backlight source according to the state of the backlight source. When the backlight source is in an on state, the charging time of the sub-pixel corresponding to the backlight source is a first charging time. When the backlight source is in an off state, the charging time of the sub-pixel corresponding to the backlight source is a second charging time, the second charging time being shorter than the first charging time.

Pixel charging method for adjusting sub-pixel charging time, pixel charging circuit, display device and display control method

A shift register circuit is provided that has an input terminal and an output terminal, and includes: an input module connected to the input terminal and a first node when the input, terminal is active, sets the first node to active; a reset module connected to the input terminal and a second node when the input terminal is active, sets the second node to inactive; an output module connected to the first node and the output terminal when the first node is active, sets the output terminal to active with a clock signal; a pull down module connected to the first node, the output terminal and the second node when the second node is active, sets the first node and the output terminal to inactive.

Shift register circuit and drive method thereof, scan drive circuit and display device

A charge pump, a voltage control method for the charge pump, and a display device are provided. The charge pump includes a voltage output end and a first step-up circuitry. The first step-up circuitry includes a first energy storage unit, a second energy storage unit, a first input control unit, a first voltage application control unit, a first output control unit and a first charging path control unit. The first voltage application control unit is configured to enable a first end of the first energy storage unit to be electrically connected to, or electrically disconnected from, a first voltage end, and enable a first end of the second energy storage unit to be electrically connected to, or electrically disconnected from, a second voltage end.

Charge pump, voltage control method for charge pump, and display device

A driving method of display panel, a display panel and a display device are disclosed. The driving method includes: in a single-frame display time, sequentially applying signals to a plurality of first sub-pixels connected to first data lines in a scanning direction so that: a signal polarity applied to each of a plurality of first white sub-pixels connected to first data lines is opposite to a signal polarity applied to a first sub-pixel which is located at an upstream of the first white sub-pixel along the scanning direction and is adjacent to the first white sub-pixel, and a signal polarity applied to each of a plurality of first colored sub-pixels is identical with a signal polarity applied to a first sub-pixel which is located at an upstream of the first colored sub-pixel along the scanning direction and is adjacent to the first colored sub-pixel.

Driving method of display panel, display panel and display device

The present disclosure provides a method and a device for driving a GOA circuit, a time controller and a display device. The method includes steps of: determining a bright-dark period for striped patterns on a display panel; and compensating for data signals at rows where the striped patterns are located periodically in accordance with the bright-dark period.

Method and device for driving GOA circuit, time controller, and display device

The present disclosure provides a level shifting unit which includes, for example, a logic control module, an output module, an output control module and a feedback module. The logic control module is connected to a turn-on power supply, a driving power supply, an input signal terminal, and the output module. The feedback module is connected to an enable signal terminal, a signal output terminal, and the output control module. The output control module is connected to the output module and the driving power supply. The output module is connected to the signal output terminal. The feedback module controls to turn on or turn off the output module through the signals outputted from the enable signal terminal and the signal output terminal. If the signals outputted by two level shifting units are short circuited, the feedback module controls the output control module of the level shifting circuit to be disconnected.

Level shifting unit, level shifting circuit, method for driving the level shifting circuit, gate driving circuit and display device

Embodiments of the present disclosure provide a clock signal transmission circuit, a driving method thereof, a gate driving circuit, and a display device. The clock signal transmission circuit includes an input circuit, a pull-up circuit, a reset circuit, a pull-down control circuit, a pull-down circuit, and a pull-up holding circuit. According to an embodiment of the present disclosure, the clock signal source can be disconnected from each shift register unit in the gate driving circuit before a screen is displayed, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.

Clock signal transmission circuit and driving method thereof, gate driving circuit, and display device

The embodiments of the disclosure provide a mobile terminal, which includes a power generation unit, a power storage unit and a control system. The power generation unit includes a toroidal inductance coil which can move back and forth inside and outside a region of magnetic field generated by a permanent magnet and incise magnetic force lines of the permanent magnet, such that a current is generated in the toroidal inductance coil. The power storage unit is connected with the toroidal inductance coil of the power generation unit and a power supply circuit of the mobile terminal, respectively, and the power storage unit is used for storing power generated by the power generation unit. The control system is connected with the power storage unit. When electricity of a battery of the mobile terminal is less than a predetermined amount and the battery is not in a charged state, the control system causes the power storage unit to supply power to the mobile terminal.

Growing community of inventors

Beijing, China

Guohuo Su