Microsemi Semiconductor Ulc

Guohui Situ

Krste Mitric

John William Mitchell Rogers

Qu Gary Jin

Paul H L M Schram

Slobodan Milijevic

Richard Geiss

Jun Steed Huang

Changhui Cathy Zhang

Tuoxin Wang

A time-to-digital converter (TDC) measures a time interval &#x394;Tbetween a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals Tdetermined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals T. A Vernier core for measures a residual time interval Twhere T=&#x394;T&#x2212;mTto obtain a value for the time interval &#x394;T. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Time-to-digital converter with phase-scaled course-fine resolution

A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.

Phase locked loop with accurate alignment among output clocks

A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.

Universal input buffer

A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio.

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Stittsville, Canada

Guohui Situ