Hangzhou Dianzi University

Hangzhou Dianzi University Fuyang Electronic Information Research Institute Co., Ltd.

Guohua Liu

Zhiqun Cheng

Zhihua Dong

Hui Liu

Jian Li

Chao Le

Xiebin Huang

Yelong Jian

Ze Qin

Huajie Ke

Shiqi Li

Songye Wang

The present disclosure provides a reconfigurable power amplifier (PA) based on a PIN switch and a design method thereof. The reconfigurable PA based on a PIN switch includes an input port, an input matching circuit, the PIN switch, a gate bias circuit, a transistor, a drain bias circuit, an output matching circuit and an output port, where the input matching network includes an input end connected to a power input end, and an output end connected to a gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain bias circuit is connected in parallel with a drain, the drain of the transistor is connected to an input end of the output matching circuit, and an output end of the output matching circuit serves as a power output.

Reconfigurable power amplifier based on pin switch and design method thereof

An enhancement-mode III-V HEMT based on an all-solid-state battery is provided. In which, a second semiconductor layer and a first semiconductor layer are sequentially formed on a substrate, and a heterostructure is formed between the second semiconductor layer and the first semiconductor layer; a source electrode is electrically connected to a drain electrode through a 2DEG generated in the heterostructure; a gate electrode is used to control on-off of the 2DEG in the heterostructure; and an all-solid-state battery is arranged between the source electrode and the gate electrode, is composed of at least one group of battery units connected in series or connected in series and parallel, and is used to deplete the 2DEG in a corresponding region of the heterostructure.

Enhancement-mode III-V HEMT based on all-solid-state battery

Disclosed is a novel III-V heterojunction field effect transistor comprising a substrate layer, a first semiconductor layer, a second semiconductor layer, a drain electrode, a source electrode, a gate electrode, a first dielectric layer, second dielectric layers and the like, wherein the first semiconductor layer has a greater bandgap compared with the second semiconductor layer, and the second semiconductor layer and the first semiconductor layer are combined to form a heterostructure. The thickness of the first semiconductor layer is not greater than the critical thickness of two-dimensional electron gas formed in a heterojunction channel, and thus natural 2DEG in the heterojunction channel is depleted. The novel III-V heterojunction field effect transistor has the advantages of being simple in structure, simple in preparation process, stable in performance, high in reliability and the like.

III-V heterojunction field effect transistor

Growing community of inventors

Hangzhou, China

Guohua Liu