Other

Hangzhou Haicun Information Technology Co., Ltd.

Chengdu Haicun IP Technology LLC

Southern University of Science and Technology

Actel Corporation, Inc.

Xiamen Haicun IP Technology LLC

Guobiao Zhang

Chengdu Haicun Technology LLC

Hangzhou Haichun Information Technology Co., Ltd.

Hangzhou Haicun Informationa Technology Co., Ltd.

Hangzhou Kicun Nformation Technology Co. Ltd.

Hong Kong Haicun Technology Co., Limited

Hongyu Yu

Chenming Hu

Chen Shen

Steve S Chiang

Yuejin Guo

Shengming Zhou

Zhitang Song

Jinfeng Kang

Wang Zhang

Peter Y Yu

Sannian Song

Guoxing Zhang

WenSheng Wang

Guangzhao Liu

Chuan Tang

Mingtao Hu

Bin Yu

Yida Li

Kai Chen

Jin He

Jun Lan

Andrew T Shih

Xiaodong Xiang

Chenchang Zhan

RangYu Deng

XiangDong Lu

XuGuang Wang

DongYun Zhang

Allison P Shih

ZhiWei Liu

Mei Shen

Yaofei Feng

Bruce Bing Wang

A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises at least a portion of a logic/processing circuit and an off-die peripheral-circuit component of the 3D-M array(s). The preferred 3-D processor can be used to compute non-arithmetic function/model. In other applications, the preferred 3-D processor may also be a 3-D configurable computing array, a 3-D pattern processor, or a 3-D neuro-processor.

Discrete three-dimensional processor

The present invention discloses an ESD protection circuit comprising resistor vias. It comprises a plurality of ESD devices connected in parallel, with each ESD device comprising a resistor and a two-terminal switch (e.g. an OTS component) connected in series. The resistor is formed in a resistor via disposed vertically with the two-terminal switch and filled with at least a conductive material with high resistivity.

Electrostatic discharge (ESD) protection circuits

High-density three-dimensional (3-D) vertical memory (3D-M) includes lightly-doped-segment (LDS) 3D-Mand non-circular-hole (NCH) 3D-M. The preferred LDS 3D-Mtakes advantage of longitudinal space, instead of lateral space, to guarantee normal write operation. On the other hand, the lateral cross-section of the memory hole of the preferred NCH 3D-Mincludes at least two intersecting pairs of parallel sides, with each pair formed through a single DUV exposure and having a minimum spacing <50 nm.

High-density three-dimensional vertical memory

A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.

Three-dimensional processor for parallel computing

A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

The present invention discloses parallel, series and hybrid ESD protection circuits. A preferred parallel ESD protection circuit comprises a plurality of ESD devices connected in parallel, with each comprising a resistor and an OTS component connected in series. A preferred series ESD protection circuit comprises a plurality of ESD devices connected in series, wherein the OTS components in all ESD devices are disposed on a same level. A preferred hybrid ESD protections circuit comprises ESD devices connected in parallel, as well as in series.

A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays and in-die peripheral-circuit components thereof, whereas the second die comprises processing circuits and off-die peripheral-circuit components of the 3D-M arrays. The first and second dice are communicatively coupled by a plurality of inter-die connections.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D random-access memory or 3-D read-only memory (3D-RAM/3D-ROM) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-RAM/3D-ROM arrays. The first die does not comprise the off-die peripheral-circuit component of the 3D-RAM/3D-ROM arrays.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). Typical off-die peripheral-circuit component could be an address decoder, a sense amplifier, a programming circuit, a read-voltage generator, a write-voltage generator, a data buffer, or a portion thereof.

A discrete three-dimensional (3-D) processor comprises stacked first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). In one preferred embodiment, the first and second dice are vertically stacked. In another preferred embodiment, the first and second dice are face-to-face bonded.

A method for making a three-dimensional (3-D) module includes the steps of: A) forming a laminate of alternate ceramic tape layers and internal electrode layers on a substrate; B) etching said laminate to form first and second capacitor stacks at said first and second locations; C) firing said first and second capacitor stacks integrally; D) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively.

Methods for making three-dimensional module

A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

A discrete three-dimensional (3-D) processor comprises first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.

A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently.

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Corvallis, OR, United States of America

Guobiao Zhang