Advanced Semiconductor Engineering, Inc.

Guo-Cheng Liao

Yi Chuan Ding

Yi-Chuan Ding

Chia-Ching Chen

Ting Ruei Chen

Yuan-Chang Su

Chun-Che Lee

Hung-Hsiang Cheng

Yun-Hsiang Tien

Chia Ching Chen

Wen-Chi Cheng

Jyun-Chi Jhan

A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.

Semiconductor device package

A semiconductor device package includes a substrate, a support structure and a first antenna. The substrate has a first surface and a second surface opposite to the first surface. The support structure is disposed on the first surface of the substrate. The first antenna is disposed on the support structure. The first antenna has a first surface facing the substrate, a second surface opposite to the first surface and a lateral surface extending between the first surface and a second surface of the first antenna. The lateral surface of the first antenna is exposed to the external of the semiconductor device package. The first antenna includes a dielectric layer and an antenna pattern disposed within the dielectric layer and penetrating the dielectric layer.

A semiconductor device package includes a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first supporting structure disposed on the first surface of the substrate and a second supporting structure disposed on the first surface of the substrate. The first supporting structure has a first surface spaced apart from the first surface of the substrate by a first distance. The second supporting structure has a first surface spaced apart from the first surface of the substrate by a second distance. The second distance is different from the first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the substrate. The first antenna is supported by the first surface of the first supporting structure and the first surface of the second supporting structure.

A package substrate includes a first dielectric layer, a first patterned conductive layer and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks of the first set of alignment marks and the first edge are different from each other.

Present disclosure provides a lead frame, including a die paddle and a plurality of leads surrounding the die paddle. Each of the leads including a finger portion proximal to the die paddle and a lead portion distal from the die paddle. The finger portion includes a main body and at least one support structure. The respective support structures on adjacent leads are mutually isolated, and a distance between the support structure and the die paddle is smaller than a distance between the lead portion and the die paddle. A semiconductor package structure including the lead frame described herein and a semiconductor package assembly including the semiconductor package structure described herein are also provided.

Semiconductor package structure

A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.

Substrate structure and semiconductor package structure including the same

A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.

Semiconductor package structure and method for manufacturing the same

A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

Semiconductor substrate and semiconductor package structure having the same

The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Semiconductor substrate and method for making the same

A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

Semiconductor packages having increased input/output capacity and related methods

A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout.

Growing community of inventors

Kaohsiung, Taiwan

Guo-Cheng Liao