Infineon Technologies Ag

Gunther Mackh

Adolf Koller

Gerhard Leschik

Rainer Leuschner

Maria Heidenblut

Carsten Ahrens

Markus Brunnbauer

Uwe Seidel

Bernhard Drummer

Harald Gossner

Georg Seidemann

Alexander Heinrich

Harald Seidl

Klemens Pruegl

Kai Esmark

Markus Menath

Berthold Schuderer

Richard Owen

Katharina Umminger

Hannes Eder

Reinhard Hess

Korbinian Kaspar

Franz Zängl

Gabriel Maier

Sven Albers

Ulrich Krumbein

Jochen Mueller

Reinhard Pufall

Sergey Ananiev

Rainer Holmer

Klaus Gnannt

Andreas Bauer

Michael Goroll

Sabine Penka

Anatoly Sotnikov

Dieter Kohlert

Patrick Schelauske

Erhard Sixt

Grit Schwalbe-Dietrich

Bernhard Duschinger

Josef Hermann

Martin Brandl

Stefan Kaiser

Kabula Mutamba

Georg Reuther

Uwe Siedel

A method of separating an electronic chip from a wafer is disclosed. In one aspect, the method comprises forming at least one trench in a back side of the wafer around at least part of the electronic chip to be separated, forming a back side metallization covering at least part of the back side and at least part of the at least one trench and attaching an adhesive layer of a tape to at least part of the back side metallization. The electronic chip is separated by removing material from a front side of the wafer along a separation path which includes part of the at least one trench in such a way that, during separating, the adhesive layer fills at least part of the at least one trench above a level of the back side metallization on the back side.

Chip separation supported by back side trench and adhesive therein

A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip.

Semiconductor chip having a crack stop structure

A semiconductor device includes an active region and a trapping region positioned peripherally with respect to the active region, the trapping region presenting trapping apertures permitting the passage of particles, the trapping apertures being in fluid communication with at least one trapping chamber for trapping the particles. A method for manufacturing the semiconductor devices from one semiconductor wafer presents semiconductor device regions to be singulated along a dicing portion line. The method includes in each semiconductor device region, making a semiconductor device precursor by making or applying at least one active element in an active region, making at least one trapping chamber and making, in a trapping region of the semiconductor device region positioned more peripherally than the active region, trapping apertures in fluid communication with the at least one trapping chamber; and singulating the semiconductor device regions by separating the semiconductor device precursors along the dicing portion lines.

Semiconductor device and method for manufacturing a plurality of semiconductive devices

According to various embodiments, a method for processing a carrier may include: forming an arrangement of defects in the carrier, wherein a surface region of the carrier is disposed over the arrangement of defects at a first surface of the carrier, wherein the arrangement of defects is configured to generate a crack structure extending from the arrangement of defects into the surface region; partially removing the carrier to remove the arrangement of defects; and separating the surface region of the carrier into a plurality of surface region portions along the crack structure.

Carrier arrangement and method for processing a carrier by generating a crack structure

A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

Wafer and method for processing a wafer

In one embodiment, an inductor has a substrate, a conductor disposed above the substrate and a seamless ferromagnetic material surrounding at least a first portion of the conductor.

System and method for integrated inductor

A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

Method of dicing a wafer and semiconductor chip

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, the separation regions being free from metal, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate.

Through substrate features in semiconductor substrates

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the substrate; forming a first opening and a second opening at least partially simultaneously through the dielectric layer over the substrate; and forming a third opening through the bottom surface of the first opening and into at least a portion of the substrate.

Semiconductor structure and method for making same

A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Chip comprising a backside metal stack

A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Chip comprising a fill structure

In one embodiment, a method of forming a semiconductor device comprises forming a groove on and/or over a first side of a substrate. A dicing layer is formed from a second side of the substrate using a laser process. The second side is opposite the first side. The dicing layer is disposed under the groove within the substrate. The substrate is singulated through the dicing layer.

Singulation processes

Growing community of inventors

Neumarkt, Germany

Gunther Mackh