Agilent Technologies, Inc.

Synaptics Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Other

Jds Uniphase Corporation

Keysight Technologies, Inc.

Arithmos, Inc.

Gunter Steinbach

Timothy P Allen

Brian Jeffrey Galloway

Robert John Miller

Thomas Allen Knotts

Carver A Mead

Stephen Bisset

Ajay Khoche

Slawomir K Ilnicki

John LeMoncheck

Ken A Nishimura

Charles E Moore

David W Gillespie

Michael Allen Robinson

Charles Francis Neugebauer

Valentin Abramzon

Jon Brunetti

A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master clock path is configured to receive an input clock and to output an output clock, each of the input and output clocks having periodically occurring interleaving periods. Each interleaving period includes timeslots corresponding to the phases of interest of the time interleaved system. The detection circuit is configured to receive the input and output clocks for each timeslot, and to detect periodic noise in the output clock introduced by the master clock path by comparing the received input and output clocks. The actuator circuit includes a controllable delay element configured to adjust a delay of the input clock through the master clock path to compensate for the periodic noise detected by the detection circuit for each timeslot.

System for compensating for periodic noise in time interleaved system

A device for driving a switch in a digital-to-analog converter (DAC) includes first and second latches, and a logic gate. The first latch is configured to store a digital input data signal according to a clock signal, and to output a first latch signal corresponding to the stored digital input data signal. The second latch is configured to store the first latch signal output by the first latch according to a logical inverse of the clock signal, and to output a second latch signal corresponding to the stored first latch signal. The logic gate is configured to perform an OR logic operation on the first latch signal and the second latch signal, the logic gate outputting a drive signal for driving a switch in the DAC connected to a current source.

Device and method for driving digital-to-analog converter

Creating a low-bandwidth channel in a high-bandwidth channel. By taking advantage of extra bandwidth in a high-bandwidth channel, a low-bandwidth channel is created by inserting extra packets. When an inter-packet gap of the proper duration is detected, the extra packet is inserted and any incoming packets on the high-bandwidth channel are stored in an elastic buffer. Observing inter-packet gaps, minimal latency is introduced in the high-bandwidth channel when there is no extra packet in the process of being sent, and the effects of sending a packet on the low-bandwidth channel are absorbed and distributed among other passing traffic.

Creating a low bandwidth channel within a high bandwidth packet stream

Systems and methods of characterizing eye diagrams are described. In one aspect, at measurement times across a measurement interval spanning at least one unit interval of the input signal, corresponding levels of the input signal are classified into groups based on at least one threshold. An eye diagram characteristic width is derived based on a distribution across the measurement interval of the levels in one of the groups.

Characterizing eye diagrams

A linear PLL includes a VCO with first and second tuning elements. The first tuning element is adjusted in proportion to the phase error between an input signal and a VCO signal and the second tuning element is adjusted by an integral function of the phase error. By configuring the VCO with separate tuning elements that are separately adjusted in proportion to the phase error and by an integral function of the phase error, the 3dB bandwidth frequency of the linear PLL depends primarily on the phase detector gain and the VCO gain that is contributed from the proportional adjustment. A linear PLL with separate proportional and integral tuning elements can be designed to exhibit a relatively constant gain over a relatively large frequency range.

Linear phase-locked loop with dual tuning elements

The frequency changes in a bang-bang PLL that are generated using a digital phase detector's up/down signal are initially set to produce a faster pull-in rate and then reduced to produce a slower pull-in rate. The faster pull-in involves relatively large frequency changes and the slower pull-in rate involves smaller frequency changes. The changes in frequency of a bang-bang PLL can be implemented using a step size controller that includes timing control logic and step size logic. The function of the timing control logic is to control the timing of step size changes. The function of the step size logic is to set the step size of the frequency changes that are made by the VCO in response to the pd_up/down signal that is delivered directly to the VCO from the digital phase detector.

Controlling a voltage controlled oscillator in a bang-bang phase locked loop

A circuit and method for receiving digital signals are disclosed. The circuit includes an input connected to a communications channel over which a digital signal is communicated and operates a plurality of multiple decision circuits at a frequency that is a fraction of the bit rate of the digital signal. A feedback and/or equalizer circuit receives the output of the decision circuits and applies a feedback signal to the input of the decision circuits that is representative of a combination of output signals of the decision circuits. The result is seen to improve the noise margin for correctly interpreting signals communicated over a communications channel having a low-pass characteristic.

System and method for providing equalization in a multiphase communications receiver

An offset related to a feedback system for a VCO is quantified and then a parameter of the feedback system is adjusted in response to the quantified offset to correct for the offset. Correcting for offset in a feedback system can improve the performance of a PLL by reducing phase drift between the input signal and the VCO signal. The reduced phase drift can have benefits such as, for example, reduced bit errors and/or improved phase tracking accuracy.

Method and system for operating a feedback system for a voltage controlled oscillator that involves correcting for offset related to the feedback system

A technique for establishing a tuning signal window for a multi-band VCO involves setting the tuning signal window to an initial size, preferably a relatively small size, and determining whether the VCO is churning. When the VCO is determined to be churning, the tuning signal window is expanded until the VCO stops churning. In an embodiment, the tuning signal window is expanded incrementally until the tuning signal window is large enough to include a solution, where a solution is defined as an operating point along a frequency band that satisfies both the setpoint frequency and tuning window signal requirements. The tuning signal window can be set at an offset relative to the tuning signal zero to compensate for shifts in the frequency bands that may result from changes in operating conditions.

Establishing a tuning signal window for use in centering a multi-band voltage controlled oscillator

A technique for correcting for DC offset in a phase locked loop involves generating digital phase information in response to an input signal and then generating an offset correction signal in response to the digital phase information. The digital phase information may include transition samples that are integrated to generate the offset correction signal. Integrating the transition samples helps to compensate for the effects of phase noise, especially phase noise that is contributed by the input signal and/or the recovered clock signal.

Correcting for DC offset in a phase locked loop

Centering a multi-band VCO involves comparing a VCO tuning signal to a pre-established tuning signal window to determine whether to change the frequency band of the multi-band VCO. The frequency band of the multi-band VCO can be changed only when the tuning signal is outside the tuning signal window. Further, the frequency band can be changed as long as the VCO is being controlled by a frequency detector. Once the multi-band VCO achieves lock, the multi-band VCO is changed by at least one more frequency band as long as the VCO tuning signal is still outside the tuning signal window.

Centering a multi-band voltage controlled oscillator

A proximity sensor system includes a sensor matrix array having a characteristic capacitance on horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by digital circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. Noise reduction and background level setting techniques inherently available in the architecture are employed.

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Palo Alto, CA, United States of America

Gunter Steinbach