Deutsche Itt Industries Gmbh

Micronas Intermetall Gmbh

General Semiconductor, Inc.

Gunter Igel

Martin Mall

Ruediger Joachim Stroh

Johann Schroeder

Siegfried Heinrich

The invention relates to a capacitor structure with two substrates ( ) each having a capacitor electrode ( ) deposited on its surface, the substrates ( ) being joined together by bump structures located on both sides of the capacitor electrodes ( ) such that the capacitor electrodes ( ) lie opposite each other and form a capacitor, the distance d between the capacitor electrodes ( ) being defined by the height of the bump structures, and measuring connections ( ) being provided on one of the substrates ( ) for making capacitance measurements.

Capacitor structure and fabrication process

The invention relates to a process for manufacturing semiconductor devices with active device structures which are connected with one another in a wafer, the area of a semiconductor device being determined by process parameters and being substantially greater than the area of an active device structure. An improvement of the process is achieved by forming several like active device structures on each of the semiconductor devices.

Process for manufacturing semiconductor devices with active structures

A process for forming adjacent moats or holes in an electrically non-insulating substrate wherein an electrically insulating masking layer is deposited on the substrate. To form two adjacent moats or holes, the masking layer has an opening whose width is chosen so that it extends over a part of the overall width of the two moats or holes to be formed, and whose shape corresponds to the shape of the moats or holes to be formed. The surface of the masked substrate is then subjected to an anodic oxidation, with the oxidation voltage chosen to be so high that two adjacent moats or holes are formed per opening in the masking layer.

Process for forming adjacent moats or holes

A process for manufacturing discrete electronic devices with active structures in an SOI (silicon-on-insulator) substrate which is thickened by an epitaxial layer and whose surface has a &lt;100&gt; orientation, said process comprising the steps of: anisotropically etching the first silicon layer to form a moat having a diameter tapering in the direction of the insulator layer, said moat extending to the insulator layer; forming an insulating layer on the sidewalls of the moat; removing a portion of the insulator layer adjoining the moat to expose a portion of the second silicon layer, which is separated from the first silicon layer by the insulator layer; forming the active structure in the second silicon layer below the portion of the insulator layer which was removed; and depositing a contact layer on the insulating layer and the active element for making contact to the active structure.

Process for manufacturing discrete electronic devices

A method identifying components is disclosed. Measured values of a randomly produced property of the component are recorded. The measured values are biuniquely assigned to the component by means of a characteristic parameter and the measured values accessibly storing the measured values, or a unique code assigned thereto. Further, the characteristic parameter are accessibly stored.

Method for identifying an apparatus or device utilizing a randomly

A process is disclosed for making contact to differently doped regions in a semiconductor device which are disposed in a silicon substrate in different depths, a first region with a first dopant concentration and/or conductivity type and the smaller depth being disposed in a second region with a second dopant concentration and/or conductivity type and the greater depth, and a first metal layer being deposited on the first region. A second metal layer is deposited on a portion of the first metal layer, and the structure is subjected to a heat treatment in which contact is made to the first region through the first metal layer and to the second region through the first metal layer and the second metal layer.

Process for making contact to differently doped regions in a

An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Process and auxiliary device for fabricating semiconductor devices

A method for separating elements associated within a body includes creating a separation region within the body, between the elements, leaving a region of the body which is to be thinned. The method then requires depositing a delay layer on the body, with an opening around the separation region. The delay layer has a predetermined removal rate relative to the removal rate of the body. Lastly, the method requires removing a predetermined amount of the delay layer, the separation region, and the region of the body to be thinned. Preferably, the removing is accomplished by etching, such as plasma etching, and the etch rate of the delay layer is lower than the etch rate for the separation region. In a preferred method, the predetermined removal rate and the positions of the openings in the delay layer are selected so that upon after etching, the elements remaining have a predetermined locus dependent thickness. Alternatively, the delay layers may be formed from the base material, formed from a metallic material or made from a silicon dioxide (SiO.sub.2) material. The base material is preferably a semiconductor wafer and the elements are semiconductor based electronic elements.

Method of separating electronic elements

A method of separating electronic devices contained in a carrier which are provided at the surface of the carrier and are covered by a protective layer. Openings are provided above separation regions between adjacent electronic devices. The material of the carrier is removed in the separation regions starting from the openings, and the electronic devices are, at least during the material-removing process, confined in the carrier by respective regions with a material removal property different from that of the carrier.

Growing community of inventors

Teningen, Germany

Gunter Igel