Infineon Technologies Ag

Infineon Technologies LLC

Gunter Haider

Uwe Weder

Gerhard Nebel

Holger Sedlak

Iker San Sebastian

Christoph Mayerl

Andreas Schlaffer

A circuit arrangement having a voltage regulator, which is designed to generate a regulated operating voltage, and a voltage monitoring unit, which is designed to monitor the regulated operating voltage for deviations from desired values. The voltage monitoring unit has a first detector, which is designed to cause an alarm signal to be generated when the first detector detects that the regulated operating voltage is outside a first voltage interval, and a second detector, which is designed to cause an initiator to initiate countermeasures which influence the regulated operating voltage when the second detector detects that the regulated operating voltage is outside a second voltage interval, which is inside the first voltage interval.

Monitor and circuit arrangement for voltage regulator

A circuit arrangement for voltage regulation having a series regulator with a regulating amplifier and a charge pump that is connected downstream of the regulating amplifier, a reference voltage unit that generates a reference voltage for the regulating amplifier, and a starter unit that generates a starter voltage in order to supply the regulating amplifier, the charge pump, and the reference voltage unit with voltage while the series regulator is being started.

Circuit arrangement for voltage adjustment

A voltage regulator having a current mirror for decoupling a partial current icluding a first NMOS transistor as a series transistor. In addition, the voltage regulator has a second NMOS transistor, which forms a current mirror with the first NMOS transistor. Furthermore, in the case of the voltage regulator, the first NMOS transistor is connected in series with a first PMOS transistor and a third transistor. The second NMOS transistor is likewise connected in series with a second PMOS transistor and a fourth transistor, the control inputs of the first and second PMOS transistors being connected to one another and the control inputs of the third and fourth transistors being connected to a control terminal for setting the magnitude of the partial current to be decoupled.

Voltage regulator with a current mirror for partial current decoupling

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Linz, Austria

Gunter Haider