Marvell International Limited

Xelerated Ab

Xelerated Newco Ab

Gunnar Nordmark

Vitaly Sukonik

Jakob Carlström

Par Westlund

Thomas Bodén

Mattias Persson

Kurt Thomas Boden

Lars-Olof B Svensson

Thomas Stromqvist

Thomas Boden

Joachim Roos

Lars-Olov Svensson

Lars-Olaf Svensson

Mikael Karpberg

A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.

System and method for modifying, in a processing pipeline, a length of a data packet in a data block without modifying a length of the data block

A network processing device comprising a plurality of programmable processors coupled together to perform a set of packet processing operations to process a packet received by the network processing device. Ones of the programmable processors being configured to perform a respective subset of the set of packet processing operations with a respective portion of a packet context such that respective programmable processors receives a portion of the packet context, that is less than a full packet context for performing the packet processing operations. The portion of a packet context being dimensioned to perform the respective subset of the packet processing operations.

Dynamic processing context

A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

Network processor unit and a method for a network processor unit

The present invention relates to a method and apparatus for pipelined processing of data. When a data packet containing information is received by a processor operating according to pipelined processing, bits are added to the data packet and an intermediate packet, comprising more bits than the received data packet, is generated. To the intermediate packet is associated information reference, the information reference comprising information regarding the length and position of the information in the intermediate packet. As the intermediate packet is processed, changes to the intermediate packet resulting in changes of the length or the position of the information in the intermediate packet will trigger changes of the information reference. When the intermediate packet exits the processor, superfluous bits are removed.

Method and apparatus for processing data in a pipeline, in which processing the length of information contained in the data packet and/or the position of the information in the data packet is altered

A method of and a network processor unit () for processing of packets in a network, the network processor () comprising: communication interface () configured to receive and transmit packets; at least one processing means () for processing packets or parts thereof; an embedded switch () configured to switch packets between the communication interface () and the processing means (); and wherein the embedded switch () is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means () for processing thereof, to receive the processed first part of the packet from the processing means (), and to transmit the processed first part of the packet.

The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronization mechanism adapted to synchronize the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronization mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.

Method and apparatus for pipelined processing of data packets

A method in a processor is presented, in which data is processed in a pipelined manner, the data being included in a plurality of contexts, comprising a first (), in addition to which a plurality of operations is adapted to be executed on the contexts. The method comprises executing an initial operation step () of a first operation on the first context (), and subsequently commencing an execution of an initial operation step () of a second operation on the first context before an execution on the first context () of a following operation step () of the first operation is completed.

Method in pipelined data processing

Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the second register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.

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Danderyd, Sweden

Gunnar Nordmark