Intel Corporation

Gunjeet D Baweja

Harsh Kumar

Kelan Craig Silvester

Marion H Shimoda

Cheng-Feng Chang

James P Kardach

John Whitley Richardson

Tim W Chan

Chin-Shu Tan

Navin Misra

An apparatus and method for branch prediction are disclosed. The branch predictor has four portions. The first includes a bimodal branch predictor in series with a local branch predictor; the second includes a global branch predictor. The first and second portions are in parallel and operate concurrently, and each provide an output received by the fourth portion. The third portion receives address data and selection data, and also provides output to the fourth portion. The fourth portion receives these outputs, and provides a branch prediction. The branch prediction is a selection of either the output from the first portion or the output from the second portion, based upon selection criteria received from the third portion.

Apparatus and method for branch prediction utilizing a predictor combination in parallel with a global predictor

A branch prediction architecture is disclosed, having a branch predictor, a target address register, first and second multiplexors, a cache memory, and a trace cache. The branch predictor may advantageously be a series-parallel branch predictor, and alternatively may be a serial-BLG branch predictor or a choosing branch predictor. The first multiplexor receives an input from the target address register, and provides an output to the cache memory. The cache memory receives output from both the branch predictor and the first multiplexor, and provides an output to the second multiplexor. The trace cache receives the output from the branch predictor, and provides an output received by the second multiplexor. The second multiplexor, receiving input from both the trace cache and the cache memory, outputs branch predictions and instruction bundles.

Branch prediction architecture

A method and apparatus for power management in a computer system is provided. A first power management signal is asserted, to indicate entry into a power management mode. An internal power management signal is generated, the internal power management signal being distinct from the first power management signal. The internal power management signal signals that a primary power connection is not stable. The primary power connection to the computer system is disconnected. The computer system is in said power management mode when the primary power connection is disconnected and the internal power management signal is asserted.

Method and apparatus for logic and power isolation during power management

The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.

Cache memory architecture with on-chip tag array and off-chip data array

The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory.

Cache memory with reduced latency

The present invention is a method and apparatus for reducing power consumption of a computer system in a suspend mode. When the computer system enters a suspend mode, the main clock is turned off and the internal oscillator is used to refresh the memory. This internal oscillator is designed such that it is only operating when the computer system is in a suspend mode. The internal oscillator is further designed such that during suspend mode, it operates only to properly refresh the memory and enter or exit the suspend mode.

Maintaining a memory while in a power management mode

A system for controlling the temperature inside a computer system housing involves determining whether a predetermined temperature set point has been exceeded. If the temperature set point has been exceeded, corrective action is attempted without adversely affecting the performance of the computer system. This may be accomplished by determining whether there are unused devices which are consuming power. If so, these devices may be transitioned to a lower power consumption state which may correspond to a lower heat generation state as well.

Controlling temperatures in computers

A method and apparatus for a memory control system is provided. The memory control system includes a first memory controller designed to access and refresh a DRAM, using a clock, during a first operation mode. The memory control system further includes a second memory controller designed to maintain the DRAM during a second operation mode and to exit from the second operation mode. During the second operation mode a clock or the clock and power is turned off to the first memory controller, and upon returning to the first operation mode, no initialization of the first memory controller is needed. Since a significant proportion of the power is consumed by the first memory controller, power savings results from employing this technique.

Method and apparatus for a memory control system including a secondary controller for DRAM refresh during sleep mode

A portable computer includes a display screen which is detachably connected to the remainder of the computer. When the screen is detached, communication may continue between the screen and the housing using one of a plurality of techniques, including infrared communications, radio frequency communications, or an extensible cable link. In this way, a display screen may be positioned at a more convenient location, for example for viewing by a plurality of viewers.

Portable computer with separable screen

An integrated circuit having a terminal for receiving a first signal, a terminal for receiving a second signal, and circuitry for generating a reset signal is disclosed. The reset signal is asserted based on a transition of the first signal when the second signal is in a predetermined state. In one embodiment the first signal is a suspend clock signal, the second signal is a suspend status signal, and the reset signal is used to reset a resume well within the integrated circuit. Thus, the integrated circuit can be used in a computer system which has a suspend mode with a resume sequence during which the resume well is reset, without requiring that the integrated circuit include an extra terminal for indicating when to reset the resume well.

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Sunnyvale, CA, United States of America

Gunjeet D Baweja