Intel Corporation

Gunjan H Pandya

Pramod Kolar

John Reginald Riley

Vivek K De

Muhammad M Khellah

Dinesh Somasekhar

Yibin Ye

Kevin X Zhang

Fatih Hamzaoglu

Zheng Guo

Uddalak Bhattacharya

Wei P Chen

Tanay Karnik

Christopher B Wilkerson

Alaa R Alameldeen

Balaji Srinivasan

Bibiche M Geuskens

Tsung-yung Jonathan Chang

Swaroop Ghosh

Ali R Farhang

Wei-Hsiang Ma

Siufu Chiu

Meterelliyoz Mesut

A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Negative bitline write assist circuit and method for operating the same

An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

Read and write apparatus and method for a dual port memory

In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Dual-port static random access memory (SRAM)

Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.

Bitline floating during non-access mode for memory arrays

Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.

Reducing minimum operating voltage through hybrid cache design

A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

Hierarchical DRAM sensing

In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.

Memory circuit

A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.

SRAM with forward body biasing to improve read cell stability

Growing community of inventors

Beaverton, OR, United States of America

Gunjan H Pandya