Samsung Electronics Co., Ltd.

Yonsei University

Skhynix Inc.

I3system Corp.

Gunhee Han

Youngcheol Chae

Seog Heon Ham

Seog-Heon Ham

In Hee Lee

Dongmyung Lee

SeungHyun Lim

Jeonghwan Lee

Ji Min Cheon

Jimin Cheon

Tae Wook Kim

Taewoong Kim

Donghyun Kim

Kwi Sung Yoo

Taewook Kim

Dong-Myung Lee

Jongill Hong

Han Joo Chung

Kunhee Cho

Yeomyung Kim

Seunghan Park

Woojun Choi

Heonjin Choi

Eunsoo Chang

Inhee Lee

Haekang Jung

Seongyeol Pyo

Jongjoo Shim

Sooho Bae

A transmitter may include a first transmission driver configured to drive a first transmission line according to a first input signal, a second transmission driver configured to drive a second transmission line according to a second input signal, a third transmission driver configured to drive a third transmission line according to a third input signal. The transmitter may further include a first active inductor circuit coupled to an output terminal of the first transmission driver, a second active inductor circuit coupled to an output terminal of the second transmission driver, and a third active inductor circuit coupled to an output terminal of the third transmission driver.

Transmitter and system including the same

The inventive concept relates to a CMOS image sensor and an operating method of the CMOS image sensor. The operating method according to an embodiment of the inventive concept includes generating photoelectrons at a photo sensor element during a first time; generating photoelectrons at the photo sensor element during a second time shorter than the first time; and sensing the photoelectrons generated at the photo sensor element. A gate voltage of a transfer transistor connected to the photo sensor element is set differently at the first time and the second time. With an embodiment of the inventive concept, a dynamic range of the CMOS image sensor increases.

Complementary metal oxide semiconductor image sensor and operating method thereof

The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Time-to-digital converter and conversion method

According to the present invention, a switched capacitor circuit comprises: an inverting amplifier for removing the offset by using a chopper stabilization circuit; a sampling unit which is connected between an input terminal and the inverting amplifier; and a feedback unit which is connected to the inverting amplifier in parallel.

Switched capacitor circuit

Provided is a neural device including at least one nano-wire. The neural device includes a nano-wire formed on a base formed on a first surface of a substrate, and an electrode pad formed on a second surface different from the first surface of the substrate and configured to output an electrical signal gained from a neural fiber through the nano-wire or apply a signal for an electric stimulus to the nano-wire. Therefore, it is possible to prevent the nano-wire from becoming embedded in an encapsulation and maximize a contact between the nano-wire and a nerve.

Neural device having via-hole connection and using at least one nano-wire

An image sensor includes an analog-to-digital converter (ADC) and a decimation filter. The decimation filter includes a first digital data generator and a second digital data generator. The first digital data generator is configured to integrate sigma-delta modulated M-bit pixel data and output N-bit pixel data based on an integration result. The second digital data generator is configured to integrate the N-bit pixel data, generate P-bit pixel data based on an integration result, and output the P-bit pixel data as decimated data.

Decimation filters, analog-to-digital converters including the same, and image sensors including the converters

In one embodiment, an analog-to-digital converter (ADC) includes a comparator and a supply circuit. The comparator is configured to compare an input signal to a reference signal. The supply circuit is configured to supply the reference signal. The supply circuit is configured to provide different circuit configurations for supplying the reference signal during different stages of analog-to-digital conversion such that the reference signal is scaled in substantially a same manner during at least two of the stages.

Analog-to-digital conversion and implementations thereof

A method of resetting a time-based CMOS image sensor may be provided, where the time-based CMOS image sensor may include a photodiode, a transfer transistor transferring photo-generated charges generated in the photodiode to a floating diffusion node and having a gate to which a ramp signal is input, and a reset transistor resetting the photodiode and the floating diffusion node. The method may include generating photo-generated charges at the photodiode, transferring the photo-generated charges to the floating diffusion node in response to a ramp signal; and resetting a reset electron potential of the photodiode to be higher than a reset electron potential of the floating diffusion node.

Method for resetting time-based CMOS image sensor

A method and apparatus are provided for sigma-delta (&#x3a3;&#x394;) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

Apparatus and method for sigma-delta analog to digital conversion

An analog-to-digital converter includes a &#xbd; powered signal generator configured to generate divided signals by successively dividing a full scale signal by 2 and output one of the divided signals, an accumulator configured to update a reference signal according to a current divided signal and a current output bit, and a comparator configured to compare the updated reference signal with an input signal and generate a next output bit.

Analog-to-digital converter for accumulating reference voltages successively divided by two

A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Switched capacitor circuit with inverting amplifier and offset unit

A sigma-delta analog-to-digital converter may include a sigma-delta modulator and a decimation filter. The sigma-delta modulator may convert a first analog input signal into a first bit stream having a first pattern using sigma-delta modulation and convert a second analog input signal into a second bit stream having a second pattern using the sigma-delta modulation. The decimation filter may integrate the number of bits having a particular value in the first bit stream, output a first digital value, calculate a bitwise complement value of the first digital value, integrate the number of bits having the particular value in the second bit stream with the bitwise complement value of the first digital value as an initial value of a second digital value, and output the second digital value.

Sigma-delta analog-to-digital converter and solid-state image pickup device

An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC) and a ramp signal generator. The APS array includes a plurality of pixels arranged in a two-dimensional matrix, wherein the APS array generates a reset signal and an image signal for each selected column of the APS array. The first ADC includes a correlated double sampling (CDS) circuit array comprising CDS circuits that are arranged for each column of the APS array, wherein the first ADC generates a digital code from a signal corresponding to the difference between the reset signal and the image signal which are generated by the CDS circuit using a ramp signal. The ramp signal generator generates the ramp signal, wherein a second ADC receives a feedback of the generated ramp signal and generates a feedback reference code, and wherein the ramp signal generator calibrates the ramp signal based on a comparison using the feedback reference code.

Image sensor using auto-calibrated ramp signal for improved image quality and driving method thereof

An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC), and a ramp signal generator. The APS array has includes a plurality of pixels of arranged in a second order two-dimensional matrix, and wherein the APS array generates a reset signal and an image signal for each pixel of selected columns. The first ADC has includes correlated double sampling (CDS) circuits for each column of the APS array, and wherein the first ADC generates a digital code corresponding to the difference between the reset signal and the image signal using an output ramp signal that is applied to the CDS circuits for each column. The ramp generator generates the output ramp signal in which a low illumination portion and a high illumination portion have different slopes.

Growing community of inventors

Goyang-si, South Korea

Gunhee Han