Samsung Electronics Co., Ltd.

Gun Ok Jung

Min Su Kim

Hoi Jin Lee

Hyoung Wook Lee

Young Min Shin

Sung Bae Park

Dae Young Moon

Ken Keon Shin

Uk Rae Cho

Ken Keon Shim

Chang Jun Choi

A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.

Footer-less NP domino logic circuit and related apparatus

A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty cycle and a flip-flop clock signal having a second duty cycle. The latch and the domino logic stages respectively operate in response to a domino clock signals derived from the first clock signal. The flip-flop operates in response to the flip-flop clock signal.

Pseudo-static domino logic circuit and apparatuses including same

A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals.

Flip-flop and semiconductor device including the same

High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.

High-speed multiplexer and semiconductor device including the same

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Yongin-si, South Korea

Gun Ok Jung