Samsung Electronics Co., Ltd.

Yonsei University

Gun-Hee Han

Seog-Heon Ham

Dong-Myung Lee

Jeong-Hwan Lee

Min-ho Kwon

Seung-Hyun Lim

Dong-Soo Kim

Hyun-surk Ryu

Yong-Suk Choi

Il-Do Kim

Ju-Seop Park

Jung-Yoon Lee

Seog-Hoon Ham

Jeong-Jin Roh

Young-jun Chang

Hyun-soo Chae

Jae-Jin Yeo

Ki-Sub Song

Jin-Min Cheon

Ji-Min Cheon

A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

Digital double sampling method, a related CMOS image sensor, and a digital camera comprising CMOS image sensor

Digital double sampling method, a related CMOS image sensor, and a digital camera comprising the CMOS image sensor

An image sensor includes a delta-sigma analog-to-digital converter (ADC) including a delta-sigma modulator (DSM) and a voltage adjusting circuit. The DSM is configured to perform delta-sigma modulation on an analog signal from a unit pixel. The delta-sigma ADC is configured to convert the analog signal to a digital signal. The voltage adjusting circuit includes a replica inverter having a same configuration as at least one inverter included in the DSM. The voltage adjusting circuit is configured to adjust a power supply voltage and an input voltage provided to the at least one inverter based on a current flowing in the replica inverter.

Image sensors and image processing systems

Disclosed are an auto focus (AF) module and a photographing apparatus employing the same. The AF module may include an AF sensor having a plurality of AF pixels and a controller. The controller receives an information regarding the amount of light respectively received by the light receiving elements of one or more of the plurality of AF pixels from the one or more of the plurality of AF pixels. The controller of the AF sensor may be configured to control the operations, e.g., the light exposure timing, of the plurality of AF pixels based on the information received from the AF pixels.

Auto focus module capable of in-pixel monitoring of amount of received light photographing apparatus using the same

A method for operating an image capture device having a sensor with an array of first and second pixels includes capturing an image a plurality of times with the second pixels to produce a corresponding second image signal, the second pixels being white pixels, capturing the image a single time with the first pixels to produce a corresponding first image signal, inputting selecting signals to the sensor via a row driver to obtain the first and second image signals from the first and second pixels, respectively, and converting the first and second image signals to respective digital values via an analog-to-digital converter.

Image capture device and method of operating the same

A complementary metal oxide semiconductor (CMOS) image sensor includes a photodiode, a switch and a comparator. The switch transfers a sensing signal to a sensing node from the photodiode. The comparator, which is directly connected to the sensing node, compares the sensing signal of the sensing node with a reference signal. The comparator outputs a signal corresponding to a voltage difference between the sensing signal and the reference signal.

CMOS image sensor and image signal detecting method thereof

A ratio-independent switched capacitor amplifier includes a first sampling circuit configured to sample a first input voltage as a first sampling voltage and to double a level of the first sampling voltage during an interval in which the first input voltage is cut off; a second sampling circuit configured to sample a second input voltage as a second sampling voltage and to double a level of the second sampling voltage during an interval in which the second input voltage is cut off; and a differential amplifier circuit configured to output a difference between the first sampling voltage and the second sampling voltage.

Ratio-independent switched capacitor amplifiers and methods of operating ratio-independent switched capacitor amplifiers

An analog-to-digital converter (ADC) includes first and second circuits, a differential amplifier, a comparator and a digital-to-analog converter (DAC). The first circuit samples a reset voltage, amplifies the sampled reset voltage, and subtracts a first reference voltage from the amplified reset voltage to produce a first difference. The second circuit samples a signal voltage, amplifies the sampled signal voltage, and subtracts a second reference voltage from the amplified signal voltage to produce a second difference. The differential amplifier produces a third difference based a comparison of the first and second differences from the first and second circuits. The comparator compares an output of the differential amplifier with at least one predetermined comparison voltage and outputs a comparison result as a digital value. The DAC is connected to the first and second circuits and the comparator, and controls the first and second reference voltages in response to the digital value.

Correlated double-sampling circuit and cyclic analog-to-digital converter including the same

A time-interleaved bandpass delta-sigma modulator is developed which includes a first adder and a second adder and a comparator. An input signal is transmitted to the first adder according to the clock frequency of each channel block, and an n channel block output uof the first adder is transmitted to the first adder and the second adder of an n+2 channel block, and an n block output vof the second adder is transmitted to the second adder of an n+2 block, and an output ythat passes through an n block comparator is transmitted to the first adder and the second adder of an n+2 block. Therefore, a modulator sequentially receives output from the comparator of each block for generating the final output y.

Time-interleaved band-pass delta-sigma modulator

A burst mode receiving apparatus having an offset compensating function and a data recovery method thereof, including an intermediate value detector to detect and output an intermediate value of an input signal input from an outside source in response to a switching control signal; an amplifier to amplify and output a difference between the input signal and a reference value; an offset compensator to generate a compensation signal having a level varied corresponding to the amplified result input from the amplifier and a compensation control signal; a summing portion to add the compensation signal and the intermediate value to output the added result as the reference value to the amplifier; and a controller to generate the switching control signal and the compensation control signal corresponding to a result obtained by analyzing the amplified result input from the amplifier and a reset signal input from the outside source.

Growing community of inventors

Goyang-si, South Korea

Gun-Hee Han