Spansion Llc.

Sandisk Technologies Inc.

Cypress Semiconductor Corporation

Western Digital Technologies, Inc.

Gulzar Ahmed Kathawala

Zhizheng Liu

Sung-Yong Chung

Mark W Randolph

Kuo-Tung Chang

Timothy J Thurgate

Kroum Stanimirov Stoev

Yi He

Wei Zheng

Darlene G Hamilton

Liam Michael Parker

Ashot Melik-Martirosian

Sheung-Hee Park

Sung-Chul Lee

Cindy Sun

Gabrielle Wing Han Leung

Sergey Anatolievich Gorobets

Yu Nan Sun

Richard M Fastow

Hidehiko Shiraiwa

Aaron Lee

Jack Frayer

Lei Xue

Ming Sang Kwan

Mrinal Kochar

Kuo Tung Chang

Amol Ramesh Joshi

Mark Joseph Dancho

An Chen

Xuguang Alan Wang

Shivananda Shetty

Edward Franklin Runnion

Harry Kuo

Sean Michael O'Mullan

Yi-Chieh Chen

Jingfeng Yuan

Tio Wei Neo

Zubin Patel

Gwyn Robert Jones

Bin Wu

John Anthony Darilek

Alok Nandini Roy

Adam Shackleton

Phuong Banh

Loi La

Yuji Mizuguchi

Yanxia (Emma) Lin

Xianmin Yi

Shuenghee Park

Yanxiang Liu

Jacob Marcantel

Anne Koh

Rick Anundson

Xiaojian Chu

Abhijit Raghunathan

Asif Arfi

Adam Noah Jacobvitz

He Yi

The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.

Recovery combining hard decoding, soft decoding and artificial codeword generation

Embodiments of the present disclosure generally relate to SSD management of non-volatile memory blocks for writing multiple data streams. The SSD may include a non-volatile memory organized into a number of superblocks. Each superblock includes a number of streamblocks. In one embodiment, a method of operating the SSD includes receiving a data stream, identifying an open superblock, identifying an available streamblock from the open superblock, and assigning the data stream to the available streamblock from the open streamblock. In another embodiment, a method of operating the SSD includes receiving a first data stream and a second data stream, writing the first data stream to the first streamblock and writing the second data stream to the second streamblock, and calculating a combined XOR parity information for the first streamblock and the second streamblock.

Block management for data streams

Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.

Parity storage management

A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives, including a staging sub-drive to receive all data from a host and a plurality of other sub-drives each associated with a respective data temperature range. A controller of the memory system is configured to route all incoming host data only to the staging sub-drive and during garbage collection each individual piece of valid data from a selected source block in a selected source sub-drive is routed to a respective one of the sub-drives. The method may include only routing host data to the staging sub-drive and only relocating valid data to sub-drives other than the staging sub-drive based on a determined temperature of valid data and a unique temperature range associated with sub-drives other than the staging sub-drive in the non-volatile memory system.

System and method of managing data in a non-volatile memory having a staging sub-drive

Apparatuses, systems, methods, and computer program products are disclosed for changing storage parameters. An integrated circuit (IC) memory element receives a command to change a value of a parameter associated with the IC memory element. A parameter includes a setting for one or more storage operations of an IC memory element. An IC memory element receives one or more data sets with a command. A data set includes an identifier associated with a parameter to be changed and a new value for the parameter. Each of one or more data sets is received at a same data rate as a command. An IC memory element writes, for each of one or more data sets, a new value for a parameter to a storage location associated with the parameter.

Changing storage parameters

Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.

Adjacent wordline disturb reduction using boron/indium implant

Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory.

Screening for reference cells in a memory

A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.

Shallow bipolar junction transistor

Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

Multi-pass soft programming

Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb

A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory

Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.

Room temperature drift suppression via soft program after erase

Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

Programming in memory devices using source bitline voltage bias

Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

Multi-phase wordline erasing for flash memory

Growing community of inventors

Santa Clara, CA, United States of America

Gulzar Ahmed Kathawala