Intel Corporation

Guluke Tong

Shenggao Li

Fulvio Spagna

Sitaraman V Iyer

Sujatha Gowder

Ji Chen

Michael V De Vita

Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.

Programmable clock data recovery (CDR) system including multiple phase error control paths

Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)

Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). in embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.

Apparatus and method for extending bandwidth and supressing phase errors in multi-phase signals

Apparatus and method for extending bandwidth and suppressing phase errors in multi-phase signals

Embodiments of the invention relate generally to the field of duty cycle correction, and more particularly to method and apparatus for correcting duty cycle of a CMOS level signal when converted from a Current-Mode-Logic (CML) to a CMOS level signal via a CML to CMOS converter. The converter comprises a first differential pair unit to receive a CML level signal; a second differential pair unit to receive the CML level signal; and an embedded differential biasing unit, coupled with the first and the second differential pair units, to adjust drive strength of the first and second differential pair units based on a duty cycle of the CML level signal. The method for correcting duty cycle of the CMOS level signal output comprises receiving by the first differential pair unit a CML level signal; receiving by the second differential pair unit the CML level signal; and adjusting drive strength of the first and the second differential pair units based on a duty cycle of the CMOS level signal.

Growing community of inventors

San Ramon, CA, United States of America

Guluke Tong