Silicon Graphics, Incorporated

Gulbin Ezer

Timothy J Van Hook

Sudhaker Rao

Ronald Nicholson

The present invention is directed to a method and system for sharing a data memory among a plurality of processors in a computer system. In the system and method of the present invention, a plurality of processors are coupled to a data memory for accessing the data memory in N-bit bandwidth. The present invention receives an active signal for accessing the data memory from the plurality of processors. A processor requesting accessing to the data memory asserts an active signal. Among the processors asserting active signals, a processor is selected as a memory master to the data memory. The present invention then transfers the N-bit wide data between the selected processor and the data memory in a time slot defined by a clock cycle. Only one processor is allowed access to the data memory during a given time slot. In the preferred embodiment of the present invention, the N-bit bandwidth is large enough to accommodate the data requirements of all the processors.

Preemptive timer multiplexed shared memory access

A media coprocessor for performing 3-D graphics, video, and audio functions. The media coprocessor is comprised of a single IC semiconductor chip which is coupled with a host processor chip, one or more memory chips, and an I/O controller chip. The media coprocessor includes a digital bitstream processor, a digital signal processor, and a display processor. An update interval, synchronized to a video frame, is defined. This update interval is divided into a number of partitions. Audio data is processed during one of the partitions. Video data is processed during another partition. And 3-D graphics is processed in another partition. Thereby, the processing is performed in a sequential, time-division multiplex scheme whereby the single media coprocessor chip processes all three partitions in a single video frame.

Media coprocessor with graphics video and audio tasks partitioned by time division multiplexing

A method and system for performing floating point operations in unnormalized format using a floating point accumulator. The present invention provides a set of floating point instructions and a floating point accumulator which stores the results of the operations in unnormalized format. Since the present invention operates on and stores floating point numbers in unnormalized format, the normalization step in the implementation of the floating point operations, which is typically required in the prior art, is readily eliminated. The present invention thus provides significant improvements in both time and space efficiency over prior art implementations of floating point operations. In digital signal processing applications, where floating point operations are used extensively for sums of products calculations, the performance improvements afforded by the present invention are further magnified by the elimination of normalization in each of numerous iterations of multiply and add instructions. A method for computing floating point operations and the circuitry used by the method are described herein.

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San Jose, CA, United States of America

Gulbin Ezer