Texas Instruments Corporation

Gul Bahar Basim

Scott Robert Summerfelt

Ted S Moise

Eugene C Davis

Serkan Kincal

An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Hydrogen passivation of integrated circuits

An integrated circuit that includes a logic region, a buffer region, and a ferroelectric capacitor region that contains ferroelectric capacitors. The integrated circuit also includes a hydrogen diffusion barrier film that overlies ferroelectric capacitors and also overlies a buffer region located between a ferroelectric capacitor region and a logic region. However, the hydrogen diffusion barrier film is removed from a portion of the logic region. Moreover, a method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers

A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

A mechanical polishing apparatus includes a polishing pad, at least one carrier head positioned over and off center relative to the polishing pad and configured for holding at least one substrate against the polishing pad within a first annular region of the polishing pad when the polishing pad is rotating. At least one conditioning head is positionable over and off center relative the polishing pad at a plurality of first positions and configured for applying a contacting surface of at least one conditioning pad against the polishing pad when the polishing pad is rotating, where the conditioning pad is applied to a second annular region of the polishing pad and moves between the plurality of first positions. In the apparatus, the diameter of the conditioning pad&#x2266;a difference between a radius of the polishing pad and a width of the first annular region.

Polish pad conditioning in mechanical polishing systems

A method of conditioning a CMP polishing pad to attain a desired thickness profile in a polished layer on a wafer is disclosed. The incoming thickness profile of the layer to be polished, the thickness profile of the polishing pad, a polish rate of layer as a function of pressure and the removal rate of polishing pad material by a conditioning block are used to compute a sweep pattern for the conditioning block which will produce a desired thickness profile on the polishing pad. The method may be applied to maintaining the desired profile on the polishing pad during the course of polishing multiple wafers. The pad profile may be adjusted to keep pressure between the pad and the wafer to a safe limit to reduce polishing defects.

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Plano, TX, United States of America

Gul Bahar Basim